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Characterization of the Performance Variation for Regular Standard Cell with Process Nonidealities

Characterization of the Performance Variation for Regular St...

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Conference on design for Manufacturability through design-Process Integration V

作者： Zhang, Hongbo du, Yuelin Wong, Martin d. F. Chao, Kai-Yuan Univ Illinois Dept ECE Urbana IL USA Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9780819485335

In IC manufacturing, the performance of standard cells often varies due to process non-idealities. Some research work on 2-d cell characterization shows that the timing variations can be characterized by the timing model.(1,2) However, as regular design rules become necessary in sub-45nm node circuit design, 1-d design has shown its advantages and has drawn intensive research interest. The circuit performance of a 1-d standard cell can be more accurately predicted than that of a 2-d standard cell as it is insensitive to layout context. This paper presents a characterization methodology to predict the delay and power performance of 1-d standard cells. We perform lithography simulation on the poly gate array generated by dense line printing technology, which constructs the poly gates of inverters, and do statistical analysis on the data simulated within the process window. After that, circuit simulation is performed on the printed cell to obtain its delay and power performance, and the delay and power distribution curves are generated, which accurately predict the circuit performance of standard cells. In the end, the benefits of our cell characterization method are analyzed from both design and manufacturing perspectives, which shows great advantages in accurate circuit analysis and yield improving.

关键词： 1-d patterning dense Line Printing Standard Cell Characterization

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Uniformity-Aware Standard Cell design with Accurate Shape Control

Uniformity-Aware Standard Cell Design with Accurate Shape Co...

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Conference on the design for Manufacturability through design-Process Integration III

作者： Zhang, Hongbo Wong, Martin d. F. Chao, Kai-Yuan deng, Liang Choi, Soo-Han Univ Illinois ECE Dept Urbana IL 61801 USA Broadcom Corp Irvine CA USA Samsung Corp Seoul South Korea

ISBN: (纸本)9780819475282

When the VLSI technology scales down to sub 40nm process node, the application of EUV is still far from reality, which forces 193nm ArF light source to be used at 32nm/22nm node. This large gap causes severe light refraction and hence reliable printing becomes a huge challenge. Various resolution enhancement technologies (RETs) have been introduced in order to solve this manufacturability problem, but facing the continuously shrinking VLSI feature size, RETs will not be able to conquer the difficulties by themselves. Since layout patterns also have a strong relationship with their own printability, therefore litho-friendly design methodology with process concern becomes necessary. In the very near future, double patterning technology (dPT) will be needed in the 32nm/22nm node, and this new process will bring major change to the circuit design phases for sure. In this paper, we try to solve the printability problem at the cell design level. Instead of the conventional 2-d structure of the standard cell, we analyze the trend of the application of 1-d cell based on three emerging double patterning technologies. Focusing on the dense line printing technology with off-axis illumination, line-end gap distribution is studied to guide our methodology for optimal cell design.

关键词： Standard Cell design 1-d patterning Gap distribution dense Line Printing double patterning

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