This paper presents an efficient architecture for two-dimensional (2-d) adaptive FIR filter architecture using the distributed arithmetic (dA) algorithm. dA-based filter architectures essentially require look-up table...
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This paper presents an efficient architecture for two-dimensional (2-d) adaptive FIR filter architecture using the distributed arithmetic (dA) algorithm. dA-based filter architectures essentially require look-up tables (LUT). In the proposed filter architecture, RAM- or ROM-based LUT is replaced by adders- and logic gates-based structure that generates the LUT value corresponding to the input. Therefore, the MAC unit requires fewer logic gates and adders in dA-based realization. In addition, the memory sharing concept in architecture reduces the delay elements. Moreover, the complexity of the LUT hardware of higher-order filters is reduced by parallelly dividing the internal MAC block for the dA decomposition which offers a higher degree of modularity and parallelism in the proposed architecture. Further, 2-d delayed lms algorithm is used for the updation of the filter coefficient weights. Furthermore, two-stage pipelining is used to reduce the critical path of the architecture and it also makes critical path delay independent of the order of the filter. ASIC synthesis results reveal the advantages of the proposed structure by reducing the area, power, AdP and EdP by 54%, 48.19%, 55% and 49%, respectively, as compared with the existing architecture for filter size 8 x 8.
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