Novel. regular, compact and easily scalable residue number system (RNS) field-programmable logic (FPL) merged architectures for the orthogonal 1ddiscrete wavelet transform (dwt) and 1d inverse discrete wavelet transf...
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Novel. regular, compact and easily scalable residue number system (RNS) field-programmable logic (FPL) merged architectures for the orthogonal 1ddiscrete wavelet transform (dwt) and 1d inverse discrete wavelet transform (Idwt) are presented. These structures halve the number of look-up tables (LUTs) required per octave, providing a sustained throughput independent of the input data and filter coefficient precision. Thy are suitable to be considered as the core of 2d dwt processors for high data rate image processing applications.
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