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IEEE Conference on Industrial Electronics and Applications (ICIEA)

作者： Hau Ngo Vijayan Asari Electrical and Computer Engineering Department United States Naval Academy Electrical and Computer Engineering Department Old Dominion University

ISBN: (纸本)9781424427994

Window-based operations such as two dimensional (2-d) convolution operations are commonly used in image and video processing applications. In this paper, a new design technique that considers the neighboring pixels within the window to detect and eliminate redundant or unnecessary computations for power reduction is presented. A novel on-chip detection technique is developed for the proposed neighborhood dependent approach (NdA) to reduce computations. In addition, data partitioning methodology is employed in the on chip buffer design support real-time operations. This NdA method is applied to different window buffering schemes and experimental results are presented.

关键词： Window-based operation FPGA Neighborhood dependent approach 2d convolution 2d filter Low power design

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AN EFFICIENT METHOd FOR GENERIC dSP IMPLEMENTATION OF dILATEd convolution 47

AN EFFICIENT METHOD FOR GENERIC DSP IMPLEMENTATION OF DILATE...

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47th IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

作者： Harinarayanan, E., V Ghanekar, Sachin Cadence Design Syst Pune Maharashtra India

ISBN: (纸本)9781665405409

dilated convolution is a well-known technique used in neural networks algorithms in AI/ML applications to increase receptive-field under analysis. dilated convolution layer has an inherent property of capturing wider context in an image and long-term temporal characteristics in an audio signal. In this paper we propose a scheme that allows efficient/generic implementation of 2d dilated convolution and stride on typical dSPs where the instruction sets are well tuned for standard 1d and 2d filtering and convolution operations. The paper analyzes and morphs the basic structures of dilated convolution computations using a decomposition method similar to polyphase decomposition to map it to a friendly and efficient standard convolution operation. The method also naturally extends to include stride as a feature for dilated convolution. Using this scheme, we publish results on Tensilica's HiFi5 platform achieving a computational cycle reduction in the order of 30X and memory reduction in the order of 150X against a standard implementation for dilation. We have also made the code available as a part of Cadence's NN Library git hub code base on HiFi5 processor.

关键词： CNN 2d convolution dilation stride

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CNN Inference: VLSI Architecture for convolution Layer for 1.2 TOPS 30

CNN Inference: VLSI Architecture for Convolution Layer for 1...

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30th IEEE International System-on-Chip Conference (SOCC)

作者： Mody, Mihir Mathew, Manu Jagannathan, Shyam Redfern, Arthur Jones, Jason Lorenzen, Thorsten Texas Instruments Inc Automot Processors Bangalore Karnataka India Texas Instruments Inc Automot Processors Dallas TX USA Texas Instruments Inc Automot Processors Houston TX USA Texas Instruments Inc Automot Processors Munich Germany

ISBN: (纸本)9781538640340

deep Learning techniques like convolutional Neural Networks (CNN) are getting popular for image classification with the broad usage spanning across automotive, industrial, medicine, robotics etc. Typical CNN network consists of multiple layers of convolutions, non-linearity, spatial pooling and fully connected layer, with 2d convolutions constituting more than 95% of overall computations. In this paper, we propose novel systolic and fully pipelined architecture for convolution layer which can scale to a high performance at a very low area. The architecture is based on innovative techniques namely vector outer product and intelligent data feeder to enable 3 levels of parallelism namely data values, outputs and inputs along with pipelining of compute elements with data movements. The proposed architecture is scalable to provide processing throughput of 64/256/512/1024 Multiplies and Add (MAC) per cycle. The architecture can run up to clock 600 MHz in low power 28 nm CMOS process node enabling performance of 1.2 Tera-Ops (TOPS).

关键词： Machine learning deep Learning convolutional Neural Network VLSI Architecture TOPS GMAC 2d convolution

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Fault migration diagnosis method for rolling bearing based on 2d convolutional neural network

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NONdESTRUCTIVE TESTING ANd EVALUATION 2024年

作者： Wang, dongliang He, Jiewei Chen, Xiangyuan Li, Ning Yang, Jin CHN Energy Yulin Energy Co Ltd Yulin Peoples R China

In recent years, the development of mechanical systems has gradually become larger and more complex. As one of the most critical components of mechanical systems, the health status of rolling bearings is crucial for the safe and orderly operation of the entire mechanical system. Therefore, this paper constructs a transfer diagnosis model based on two-dimensional convolutional neural networks, achieving efficient and fast cross working condition fault transfer diagnosis of rolling bearings. In summary, this article takes rolling bearings as the research object and constructs a fault diagnosis model under working condition migration by combining two-dimensional convolutional neural networks with maximum mean difference. Based on the constructed model, experiments are designed and signal data is collected for model training, validation, and testing. This article aims to achieve cross working condition transfer diagnosis of rolling bearings by combining the constructed model with real data from the test bench, providing reference and guidance for cross domain fault diagnosis of rolling bearings in practical engineering. The research results indicate that the constructed transfer diagnosis model based on two-dimensional convolutional neural network has achieved efficient and fast fault transfer diagnosis of rolling bearings across working conditions. The accuracy of the model in the frequency domain of transfer under 6 working conditions is higher than 98.15%.

关键词： 2d convolution rolling bearings transfer learning maximum mean difference

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Real-time approximate and combined 2d convolvers for FPGA-based image processing

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JOURNAL OF SUPERCOMPUTING 2023年第16期79卷 18910-18946页

作者： Ramezanzad, Ali Rezaei, Mehran Nikmehr, Hooman Kalbasi, Mahdi Univ Isfahan Fac Comp Engn Esfahan Iran

convolution widely has been used as the main part of the improvement in digital image processing applications. In convolutional computations, a large number of memory accesses and a huge amount of computations challenge its performance. Many of the related proposed convolvers are based on exact computations. Although exact convolvers keep the accuracy of the convolution operation at the top level, sometimes by missing a negligible amount of accuracy, the performance can be improved. Approximate computing is a new technique for solving computation overhead problems. In this paper, approximate 2d convolvers are presented which minimize the memory access rate and computations by a special factor of multiply-and-accumulate (MAC) terms. On the other hand, to preserve the flexibility for supporting different required accuracy, the proposed approximate convolvers are combined with the exact designs with real-time pre-processing stages by exploiting innovative methods which manage the hardware overhead. In comparison with conventional convolvers, the proposed designs improve the number of active resources which causes a significant reduction in power consumption. For 3 x 3 kernel size, the evaluation results on the Xilinx Virtex-7 (XC7V2000t) FPGA device show 34% and 20% power optimization of the proposed approximate and combined convolvers, respectively, in comparison with exact convolver (EC). Also, this improvement grows by increasing the kernel size. Finally, a comparison based on RMSE and PSNR for different sample images and filters reveals that the error rate and image quality reduction are acceptable for many real-time image processing applications.

关键词： 2d convolution Approximate convolver Real-time image processing Power consumption Resource utilization FPGA

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design of a systolic-pipelined architecture for real-time enhancement of color video stream based on an illuminance-reflectance model

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INTEGRATION-THE VLSI JOURNAL 2008年第4期41卷 474-488页

作者： Ngo, Hau T. Asari, Vijayan K. Zhang, Ming Z. Tao, Li Old Dominion Univ Dept Elect & Comp Engn Computat Intelligence & Machine Vis Lab Norfolk VA 23529 USA

A high performance digital architecture for the implementation of a nonlinear image enhancement technique is proposed in this paper. The image enhancement is based on an illuminance-reflectance model which improves the visual quality of digital images and video captured under insufficient or non-uniform lighting conditions. The algorithm shows robust performance with appropriate dynamic range compression, good contrast, accurate and consistent color rendition. The algorithm contains a large number of complex computations and thus it requires specialized hardware implementation for real-time applications. Systolic, pipelined and parallel design techniques are utilized effectively in the proposed FPGA-based architectural design to achieve real-time performance. Approximation techniques are used in the hardware algorithmic design to achieve high throughput. The video enhancement system is implemented using Xilinx's multimedia development board that contains a VirtexII-X2000 FPGA and it is capable of processing approximately 63 Mega-pixels (Mpixels) per second. (C) 2007 Elsevier B.V. All rights reserved.

关键词： nonlinear image enhancement logarithmic approximation 2d convolution quadrant symmetry real-time video processing system systolic pipelined architecture

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Systolic hand gesture recognition/detection system based on FPGA with multi-port BRAMs

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ALEXANdRIA ENGINEERING JOURNAL 2019年第3期58卷 841-848页

作者： Salim, Ula Tarik dawwd, Shefa Abdulrahman Univ Mosul Comp Engn Dept Mosul Iraq

A new systolic approach of real-time vision-based hand gesture recognition is proposed. Hand gesture recognition is classified into two type, static and dynamic. The proposed system can be employed in both types. The system can detect and classify either a static hand shape in one image or a static hand shape at the start, within, and the end of gesture in a dynamic sequence in video stream. An efficient template matching (TM) based similarity measure is used to recognize gesture within the inter frame sequence of video frames. The template can be used to store the static class of different hand gesture shapes, while fast scanning approach of window over an image frame dynamically detects or recognizes the hand gesture. A suitable hardware systolic model of TM is designed. The systolic architecture is expanded to be used with multiple windows (k-templates) simultaneously. The required templates are equal to the number (k) of gestures that is to be recognized. They are stored in FPGA RAM blocks (BRAMs). To increase the bandwidth of templates BRAMs, the BRAM is multi-ported. A considerable reduction of memory access operations is achieved for the parallel systolic model in comparison to sequential/parallel software models. Consequently, the hand gesture is detected, tracked and recognized within the inter frame space of video. An acceptable recognition accuracy of up to 95% is achieved under variant observation conditions of three hand gesture classes dataset. A high frame rate video can be processed in real time. (C) 2019 The Authors. Published by Elsevier B.V. on behalf of Faculty of Engineering, Alexandria University.

关键词： 2d convolution Sliding window Systolic array Template matching FPGA

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Partitioning and gating technique for low-power multiplication in video processing applications

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MICROELECTRONICS JOURNAL 2009年第11期40卷 1582-1589页

作者： Ngo, Hau T. Asari, Vijayan K. USN Acad Dept Elect & Comp Engn Annapolis MD 21402 USA Old Dominion Univ Dept Elect & Comp Engn Norfolk VA 23529 USA

In this paper, we propose a partitioning and gating technique for the design of a high performance and low-power multiplier for kernel-based operations such as 2d convolution in video processing applications. The proposed technique reduces dynamic power consumption by analyzing the bit patterns in the input data to reduce switching activities. Special values of the pixels in the video streams such as zero, repeated values or repeated bit combinations are detected and data paths in the architecture design are disabled appropriately to eliminate unnecessary switching. Input pixels in the video stream are partitioned into halves to increase the possibility of detecting special values. It is observed that the proposed scheme helps to reduce dynamic power consumption in the 2d convolution operations up to 33%. (C) 2009 Elsevier Ltd. All rights reserved.

关键词： Low-power multiplication Partitioning and gating dynamic power 2d convolution Switching activities

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A tunable high-performance architecture for enhancement of stream video captured under non-uniform lighting conditions

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MICROPROCESSORS ANd MICROSYSTEMS 2008年第7期32卷 386-393页

作者： Zhang, Ming Z. Seow, Ming-Jung Tao, Li Asari, Vijayan K. Old Dominion Univ Dept Elect & Comp Engn Computat Intelligence & Machine Vis Lab Norfolk VA 23529 USA

A novel architecture for performing hue-saturation-value (HSV) domain enhancement of digital color images captured under non-uniform lighting conditions is proposed in this paper for video streaming applications. The approach promotes log-domain computation to eliminate all multiplications, divisions and exponentiations utilizing the compact high-speed logarithmic estimation modules. An optimized quadrant symmetric architecture is incorporated into the design of homomorphic filter for the enhancement of intensity value. Efficient modules are also presented for conversion between RGB and HSV color spaces with tunable H and S components in HSV for more flexible color rendering. The design is able to bring out details hidden in shadow regions of the image and preserve the bright parts with adjustable vividness and color shift for improvement of visual quality while maintaining its consistency. It is capable of producing 187.86 million outputs per second (MOPs) on Xilinx's Virtex II XC2V2000-4ff896 field programmable gate array (FPGA) at a clock frequency of 187.86 MHz. It can process over 179.1 (1024 x 1024) frames per second, which is very suitable for high definition videos, and consumes approximately 70.7% and 76.8% less hardware resource with 127% and 280% performance boost when compared to the designs with machine learning algorithm in [M.Z. Zhang, M.J. Seow, V.K. Asari, A high performance architecture for color image enhancement using a machine learning approach, International journal of Computational intelligence Research - Special Issue on Advances in Neural Networks 2(1) (2006) 40-47], and with separated dynamic and contrast enhancements in [H.T. Ngo, M.Z. Zhang, L. Tao, V.K. Asari, design of a high performance architecture for real-time enhancement of video stream captured in extremely low lighting environment, International journal of Embedded Systems: Special Issue on Media and Stream Processing, in press], respectively. This approach also provide 83.4 time

关键词： Nonlinear color image enhancement Reflectance-illuminance model HSV-domain components rendering Color space conversion Log-domain computation 2d convolution Parallel-pipelining Multiplier-less architecture Homomorphic filter Quadrant symmetric architecture

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Approximation analysis of CNNs from a feature extraction view

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ANALYSIS ANd APPLICATIONS 2024年第3期22卷 635-654页

作者： Li, Jianfei Feng, Han Zhou, ding-Xuan City Univ Hong Kong Dept Math Kowloon Tong Tat Chee Ave Hong Kong Peoples R China Univ Sydney Sch Math & Stat Sydney NSW 2006 Australia

deep learning based on deep neural networks has been very successful in many practical applications, but it lacks enough theoretical understanding due to the network architectures and structures. In this paper, we establish some analysis for linear feature extraction by a deep multi-channel convolutional neural networks (CNNs), which demonstrates the power of deep learning over traditional linear transformations, like Fourier, wavelets, redundant dictionary coding methods. Moreover, we give an exact construction presenting how linear features extraction can be conducted efficiently with multi-channel CNNs. It can be applied to lower the essential dimension for approximating a high-dimensional function. Rates of function approximation by such deep networks implemented with channels and followed by fully connected layers are investigated as well. Harmonic analysis for factorizing linear features into multi-resolution convolutions plays an essential role in our work. Nevertheless, a dedicate vectorization of matrices is constructed, which bridges 1d CNN and 2d CNN and allows us to have corresponding 2d analysis.

关键词： deep learning convolutional neural networks 2d convolution approximation theory feature extraction

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