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11th Asia-Pacific Conference on Advances in Computer Systems Architecture

作者： Zhang, Ming Z. Tao, Li Seow, Ming-Jung Asari, Vijayan K. Old Dominion Univ Dept Elect & Comp Engn Computat Intelligence & Machine Vis Lab Norfolk VA 23529 USA

ISBN: (纸本)3540400567

A novel architecture for performing digital color image enhancement based on reflectance/illumination model is proposed in this paper. The approach promotes the log-domain computation to eliminate all multiplications, divisions and exponentiations utilizing the approximation techniques for efficient estimation of 1092 and inverse-1092. A new quadrant symmetric architecture is also incorporated into the design of homomorphic filter to achieve very high throughput rate which is part of V component enhancement in Hue-Saturation-Value (HSV) color space. The pipelined design of the filter features the flexibility in reloading a wide range of kernels for different frequency responses. A generalized architecture of max/min filter is also presented for efficient extraction of V component. With effective color space conversion, the HSV-domain image enhancement architecture is able to achieve a throughput rate of 182.65 million outputs per second (MOPS) or equivalently 52.8 billion operations per second on Xilinx's Virtex II XC2V2000-4ff896 field programmable gate array (FPGA) at a clock frequency of 182.65 MHz. It can process over 174.2 mega-pixel (1024 x 1024) frames. per second and consumes approximately 70.7% less hardware resource when compared to the design presented in [10].

关键词： color image enhancement reflectance/illumination model HSV-domain image processing log-domain computation 2d convolution multiplier-less architecture homomorphic filter quadrant symmetric architecture parallel-pipelined architecture

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Systolic-based 2d convolver for CNN in FPGA 15

Systolic-based 2D convolver for CNN in FPGA

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15th IEEE International Conference on Emerging eLearning Technologies and Applications (ICETA)

作者： Hrabovsky, J. Segec, P. Moravcik, M. Papan, J. Univ Zilina Fac Management Sci & Informat Univ 8215-1 Zilina 01026 Slovakia

ISBN: (纸本)9781538632963

convolution is a primary mathematical operation used in many signal processing and analysis algorithms. High dependence of the complex systems on the correct operation of the convolver demands its continual improvements mostly related to the decrease of resource consumption. The paper proposes a model of 2d convolution massively used in the algorithms of image processing. The paper provides a detailed description of the model structure with focus on the implementation aspect. The model is particularly applied to the convolutional layer of convolutional Neural Network, currently the most known image-based deep learning method. The key difference of the proposed model compared with other common implementations lies in the placement of line buffers. The correctness of the model design is validated through the simulation discussed at the end of paper.

关键词： 2d convolution FPGA CNN systolic array

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CLTune: A Generic Auto-Tuner for OpenCL Kernels 9

CLTune: A Generic Auto-Tuner for OpenCL Kernels

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9th IEEE International Symposium on Embedded Multicore/Manycore Systems-on-Chip (MCSoC)

作者： Nugteren, Cedric Codreanu, Valeriu SURFsara HPC Ctr Amsterdam Netherlands

ISBN: (纸本)9781479986705

This work presents CLTune, an auto-tuner for OpenCL kernels. It evaluates and tunes kernel performance of a generic, user-defined search space of possible parameter-value combinations. Example parameters include the OpenCL workgroup size, vector data-types, tile sizes, and loop unrolling factors. CLTune can be used in the following scenarios: 1) when there are too many tunable parameters to explore manually, 2) when performance portability across OpenCL devices is desired, or 3) when the optimal parameters change based on input argument values (e.g. matrix dimensions). The auto-tuner is generic, easy to use, open-source, and supports multiple search strategies including simulated annealing and particle swarm optimisation. CLTune is evaluated on two GPU case-studies inspired by the recent successes in deep learning: 2d convolution and matrix-multiplication (GEMM). For 2d convolution, we demonstrate the need for auto-tuning by optimizing for different filter sizes, achieving performance on-par or better than the state-of-the-art. For matrix-multiplication, we use CLTune to explore a parameter space of more than two-hundred thousand configurations, we show the need for device-specific tuning, and outperform the clBLAS library on NVIdIA, AMd and Intel GPUs.

关键词： parallel programming public domain software software libraries 2d convolution CLTune GPU OpenCL kernels auto-tuner matrix-multiplication open-source convolution Kernel Performance evaluation Search problems Simulated annealing Tuners Auto-Tuning GEMM OpenCL convolution open source open source software Software libraries tabu search simulated annealing GRAPPER PICK UP Graphics Processing Unit Self tuning Parallel programming Kernel Performance Evaluation Seeds Tuner device Component

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Real-time Object detection with FPGA Using CenterNet

Real-time Object Detection with FPGA Using CenterNet

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IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)

作者： Solovyev, Roman A. Telpukhov, dmitry, V Romanova, IrMa I. Kustov, Alexander G. Mkrtchan, Ilya A. Russian Acad Sci IPPM RAS Inst Design Problems Microelect Moscow Russia Natl Res Univ Higher Sch Econ Moscow Russia

ISBN: (纸本)9781665404761

the paper proposes methodology for transferring architecture of modern neural network CenterNet to FPGA. CenterNet is a OneStage object detector that is used to detect and locate objects in images. Although this neural network has simple decoder, it shows good performance in terms of accuracy. Very high operation speed of the neural network hardware is achieved due to the choice of suitable encoder and efficient hardware implementation of both the decoder and the last layer with object filtering, and also transition to fixed-point arithmetic. At this, quality of the obtained predictions remains high.

关键词： Neural network hardware Field programmable gate arrays Fixed-point arithmetic 2d convolution Object detection

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Using dSP-ASIP for Image Processing Applications

Using DSP-ASIP for Image Processing Applications

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Computing Conference

作者： Sohail, Sameed Saeed, Ali Rashid, Haroon Ur Pakistan Inst Engn & Appl Sci PIEAS Dept Elect Engn Islamabad Pakistan Linkoping Univ Dept Elect Engn Linkoping Sweden

ISBN: (纸本)9783030011741;9783030011734

The rapid deployment of embedded image processing applications have forced a paradigm shift from complete hardware and software based implementations providing best performance and lowest cost, respectively towards a hybrid approach, namely, application specific instruction-set processor (ASIP). In this paper, we evaluate the applicability of CuSP, a softcore dSP-ASIP, for image processing applications. CuSP has a Crimson dSP processor core and hardware accelerators directly coupled with the core offering improved performance with flexibility. Results show that CuSP offers performance improvement over standard softprocessor MicroBlaze by up to a factor of 36 times. Crimson dSP core alone gives up to 5.3 times lower execution cycles than MicroBlaze.

关键词： dSP-ASIP Image processing 2d convolution

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Real-Time Sub-Pixel Registration of Imagery for an IR Polarimeter

Real-Time Sub-Pixel Registration of Imagery for an IR Polari...

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Conference on Polarization - Measurement, Analysis, and Remote Sensing X

作者： Hanks, Jonathan B. Pezzaniti, J. Larry Chenault, david B. Romano, Joao M. Polaris Sensor Technol Inc 200 Westside SqSuite 320 Huntsville AL 35801 USA ARDEC Trenton NJ 0780 USA

ISBN: (纸本)9780819490421

In imaging polarimetry, special consideration must be given to ensure proper spatial registration between frames. Edge artifacts caused by the differencing of unregistered frames has the potential to create significant spurious polarization signatures. To achieve 1/10(th) pixel registration or better, a software based registration approach is often required. The focus of this paper is to present an efficient algorithm for real time sub-pixel registration in a division-of-time IR polarimeter based on a rotating polarizer. This algorithm has been implemented in a commercially available rotating polarizer LWIR imaging polarimeter offered by Polaris Sensor Technologies. This paper presents measurements of image nutation in a rotating polarizer LWIR imaging polarimeter and real-time registration of image data from that same polarimeter. The registration algorithm is based on an optimal 2d convolution. Examples of registered images are provided as well as estimates of residual misregistration artifacts.

关键词： Polarimetry Polarization IR imaging Registration 2d convolution

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Spectral-Spatial Hyperspectral Unmixing Method Based on the convolutional Autoencoders 10th

Spectral-Spatial Hyperspectral Unmixing Method Based on the ...

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10th International Conference on Communications, Signal Processing, and Systems

作者： Kong, Fanqiang Chen, Mengyue Cao, Tongbo Meng, Yuxin Nanjing Univ Aeronaut & Astronaut Coll Astronaut Nanjing 210016 Peoples R China

ISBN: (纸本)9789811903908;9789811903892

Considering that hyperspectral images have lavish spectral information, they also have spatial correlation information, a spectral-spatial unmixing method based on two-dimensional convolution autoencoder is proposed in this article. The hyperspectral image first passes through the convolutional layers to obtain the spatial features, and then concatenated to itself to retain the spectral information, at this time, a spectral-spatial tensor is acquired, finally it passes through the fully connected layers to realize the linear unmixing of the hyperspectral image. For the loss function, introduce reconstruction error constraints and abundance sparsity constraints to ensure that the abundance result has physical meaning. Experimental results demonstrate that the proposed method is superior to other sparse algorithms in terms of SRE results and visual effects.

关键词： Hyperspectral unmixing Spectral-spatial feature 2d convolution deep learning

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doubly-Block Circulant Kernel Matrix Exploitation in convolutional Accelerators 66

Doubly-Block Circulant Kernel Matrix Exploitation in Convolu...

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2023 IEEE 66th International Midwest Symposium on Circuits and Systems, MWSCAS 2023

作者： Ferreira, Lucas Malkowsky, Steffen Persson, Patrik Astrom, Karl Liu, Liang Lund University Electrical and Information Technology Department Sweden Lund University Mathematics Department Sweden

ISBN: (纸本)9798350302103

In this paper, we present a novel algorithmic and hardware co-design approach specifically tailored for efficient 2d convolution implementations, a crucial operation in convolutional neural networks (CNNs). Our method addresses the limitations of existing software-based solutions and hardware-based architectures, delivering significant improvements in asymptotic behavior for generic convolution cases. By leveraging the distinctive geometry of doubly block circulant unrolled kernel matrices, our approach eliminates the need for input and weight buffers, optimizes output memory usage, and minimizes redundant memory accesses. A comprehensive comparative analysis with state-of-the-art techniques showcases the key advantages and superior performance of our proposed method, achieving substantial reductions in memory requirements and high throughput. © 2023 IEEE.

关键词： 2d convolution doubly-Blocked Circulant Matrix Systolic Array Unrolled Kernel Matrix

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AttSec: protein secondary structure prediction by capturing local patterns from attention map

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BMC BIOINFORMATICS 2023年第1期24卷 183-183页

作者： Kim, Youjin Kwon, Junseok Chung Ang Univ Dept Artificial Intelligence Seoul South Korea LG AI Res Seoul South Korea

Background: Protein secondary structures that link simple 1d sequences to complex 3d structures can be used as good features for describing the local properties of protein, but also can serve as key features for predicting the complex 3d structures of protein. Thus, it is very important to accurately predict the secondary structure of the protein, which contains a local structural property assigned by the pattern of hydrogen bonds formed between amino acids. In this study, we accurately predict protein secondary structure by capturing the local patterns of protein. For this objective, we present a novel prediction model, AttSec, based on transformer architecture. In particular, AttSec extracts self-attention maps corresponding to pairwise features between amino acid embeddings and passes them through 2d convolution blocks to capture local patterns. In addition, instead of using additional evolutionary information, it uses protein embedding as an input, which is generated by a language model. Results: For the ProteinNet dSSP8 dataset, our model showed 11.8% better performance on the entire evaluation datasets compared with other no-evolutionary-information-based models. For the NetSurfP-2.0 dSSP8 dataset, it showed 1.2% better performance on average. There was an average performance improvement of 9.0% for the ProteinNet dSSP3 dataset and an average of 0.7% for the NetSurfP-2.0 dSSP3 dataset. Conclusion: We accurately predict protein secondary structure by capturing the local patterns of protein. For this objective, we present a novel prediction model, AttSec, based on transformer architecture. Although there was no dramatic accuracy improvement compared with other models, the improvement on dSSP8 was greater than that on dSSP3. This result implies that using our proposed pairwise feature could have a remarkable effect for several challenging tasks that require finely subdivided classification. Github package URL is https://***/youjin-ddAI/AttSec.

关键词： Protein secondary structure Computational biology Transformer 2d convolution

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Object Proposal Generation Using Two-Stage Cascade SVMs

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IEEE TRANSACTIONS ON PATTERN ANALYSIS ANd MACHINE INTELLIGENCE 2016年第1期38卷 102-115页

作者： Zhang, Ziming Torr, Philip H. S. Xidian Univ Sch Comp Sci Xian 710071 Peoples R China Boston Univ Dept Elect & Comp Engn Boston MA 02215 USA Univ Oxford Dept Engn Sci Oxford OX1 3PJ England

Object proposal algorithms have shown great promise as a first step for object recognition and detection. Good object proposal generation algorithms require high object detection recall rate as well as low computational cost, because generating object proposals is usually utilized as a preprocessing step. The problem of how to accelerate the object proposal generation and evaluation process without decreasing recall is thus of great interest. In this paper, we propose a new object proposal generation method using two-stage cascade support vector machines (SVMs), where in the first stage linear filters are learned for predefined quantized scales/aspect-ratios independently, and in the second stage a global linear classifier is learned across all the quantized scales/aspect-ratios for calibration, so that all the windows from the first stage can be compared properly. The windows with highest scores from the second stage are kept as inputs to our new efficient proposal calibration algorithm to improve their localization quality significantly, resulting in our final object proposals. We explain our scale/aspect-ratio quantization scheme, and investigate the effects of combinations of l(1) and l(2) regularizers in cascade SVMs with/without ranking constraints in learning. Comprehensive experiments on VOC2007 dataset are conducted, and our method is comparable with the current state-of-the-art methods with much better computational efficiency.

关键词： Object proposal generation scale/aspect-ratio quantization cascade SVMs linear filters 2d convolution

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