An efficient hardware architecture is presented for computing convolutions and correlations with two or more dimensions. This is derived from combining a class of polynomial transforms with currently available VLSI co...
详细信息
An efficient hardware architecture is presented for computing convolutions and correlations with two or more dimensions. This is derived from combining a class of polynomial transforms with currently available VLSI convolution devices. The proposed method is particularly suitable for computing high order convolutions with little or no arithmetic quantisation errors.
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