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An FPGA Implementation of Multi-stream Tracking Hardware using 2d simd array (Abstract Only) 15

An FPGA Implementation of Multi-stream Tracking Hardware usi...

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Proceedings of the 2015 ACM/SIGdA International Symposium on Field-Programmable Gate arrays

作者： Ryota Takasu Yoichi Tomioka Takashi Aoki Hitoshi Kitazawa Tokyo University of Agriculture and Technology Tokyo Japan NTT Device Technology Laboratories Kanagawa Japan

ISBN: (纸本)9781450333153

Worldwide, many surveillance systems are in operation for crime deterrence purposes. An effective system should be characterized by requiring low-power consumption, a small storage capacity, and little human effort. Multi-stream tracking on field programmable gate array (FPGA) is important for such surveillance systems. In this paper, we propose multi-stream tracking hardware that can extract moving objects and their motion vectors from a multi-stream received from 64 cameras in real time. The key technology for multi-stream processing is as follows. (1) In order to avoid maintaining the background, we apply a frame difference method. Moreover, the flows of object are calculated by block matching. The flows are effective for analyzing human motion. (2) In order to avoid a bus bottleneck and memory contention in the communication between processing elements (PEs), synchronous shift data transfer (SSdT), which transfers data in the same direction for all PEs, is applied. In this paper, an extended SSdT is proposed for communication between PEs when multi-blocks are processed in one PE. (3) C++ based integrated control code development tool is shown. Control code written in C++ language can easily be assembled and verified by the tool. We implemented the proposed hardware on a Stratix V 5SGXEA7K2F40C2N device. The operating frequency is 50 MHz and the average number of clocks for processing a set of four frames of QVGA images is 394k clocks. The proposed hardware achieved 520 fps, and can process multi-stream video from 64 cameras. The execution time on 3.4 GHz Core i7-3770 CPU was 8.4 fps. Therefore, the proposed hardware was about 62 times faster than that CPU.

关键词： multi-stream tracking fpga 2d simd array processor synchronous shift data transfer

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An FPGA-Based Accelerator for the 2d Implicit FdM and Its Application to Heat Conduction Simulations (Abstract Only) 15

An FPGA-Based Accelerator for the 2D Implicit FDM and Its Ap...

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Proceedings of the 2015 ACM/SIGdA International Symposium on Field-Programmable Gate arrays

作者： Yutaro Ishigaki Ning Li Yoichi Tomioka Akihiko Miyazaki Hitoshi Kitazawa Tokyo University of Agriculture and Technology Tokyo Japan NTT Device Technology Laboratories Kanagawa Japan

ISBN: (纸本)9781450333153

Field-programmable gate arrays (FPGAs) are extremely advanced with regard to high performance; they are becoming one of the primary device choices to realize high-performance computing (HPC). In this work, we propose an FPGA-based accelerator for the two-dimensional (2d) finite difference method (FdM) with the implicit scheme and implement a 2d unsteady-state heat conduction simulation using red/black successive over-relaxation (SOR). The accelerator consists of a 2d single-instruction multiple-data (simd) array processor, which has pipelined processing elements (PEs) including 32-bit floating point calculation units. This processor can avoid the memory-access bottleneck and perform with high operating efficiency and low waiting time for data transfer by applying the proposed control method with synchronous shift data transfer. We demonstrate that the experimental hardware implemented on an Altera Stratix V FPGA (5SGSMd5K2F40C2N) reaches a 99.83% operating rate of the calculation units for the computation of red/black SOR. In addition, it is approximately six times faster than GPU computing on an NVIdIA GeForce GTX 770 for a 32-bit floating-point calculation of a printed circuit board (PCB) heat conduction simulation, and it is about eight times faster than an NVIdIA Tesla C2075 for the same calculation.

关键词： 2d unsteady-state heat conduction finite difference method red/black sor 2d simd array processor parallel processing fpga

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