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Investigation of interface trap characteristics in 3d nand flash memory with temperature dependency

JAPANESE JOURNAL OF APPLIEd PHYSICS 2025年第3期64卷 031004-031004页

作者： So, donghyuk Cho, Yonggyu Shim, Hyunyoung Sim, Jaesung Shin, Hyungcheol Seoul Natl Univ Interuniv Semicond Res Ctr Dept Elect & Comp Engn Seoul 08826 South Korea SK Hynix Inc NAND Tech Dev Div Team Icheon Si 17336 South Korea Integra Semicond Ltd Seoul 06970 South Korea

In this paper, the characteristics of interface traps (Nit) at poly-Si and bandgap-engineered tunneling oxide (BE-TOX) interface in 3d nand flash memory were investigated at various temperatures. Program and erase (P/E) cycling tests were carried out up to 30 k with four different temperatures and a recovery test for 60 min was conducted. The interface traps were analyzed using both the subthreshold swing (SS) method and technology computer-aided design (TCAd) simulation. Nit generation occurs due to cold hole (CH) tunneling and is explained by the reaction-diffusion (Rd) model. The Nit generation follows a power-law relation with respect to the cycle counts. Additionally, Nit recovery behavior was well fitted to the stretched exponential function (SEF). The activation energy (Ea) was extracted from the recovery behavior. Also, temperature-dependent hydrogen diffusion tendencies in the BE-TOX layer were observed through TCAd simulation.

关键词： 3d nand flash memory bandgap-engineered tunneling oxide endurance recovery interface traps program/erase cycling

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Investigation of Inhibited String Characteristics According to dimple Structures in 3d nand flash memory

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON dEVICE LETTERS 2025年第3期46卷 409-411页

作者： Park, Jesun Kang, Myounggon Univ Seoul Dept Intelligent Semicond Engn Seoul South Korea Univ Seoul Sch Adv Fus Studies Dept Intelligent Semicond Engn Seoul 02504 South Korea

In this paper, we investigated the boosted channel potential ( V-ch ) in inhibited strings with dimple (concave and convex) structures and analyzed the program (PGM) disturbance caused by V-ch . In concave structures, the electric field (e-field) concentrated in the spacer (SP) region, resulting in a decrease in V-ch as the degree of concavity increases. In convex structures, the e-field concentrates in the center of the word line (WL) region, boosting V-ch as the degree of convexity increases. This occurs due to the dispersion or concentration of the PGM voltage applied to the WL. High V-ch in the selected WL increases the potential difference (delta V-ch ) between adjacent WLs. due to structural characteristics, the lateral e-field (E-m) is largest in concave structures, whereas the vertical e-field (E-ox) dominates in convex structures. Consequently, PGM disturb characteristics caused by hot carrier injection (HCI) are significantly degraded in convex structures.

关键词： flash memories Three-dimensional displays Electrons Electric potential Shape Hot carrier injection Mathematical models deformation Artificial intelligence Tunneling 3d nand flash memory dimple channel potential HCI program disturb

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Improving cell current in 3d nand flash memory with fixed oxide charge

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SOLId-STATE ELECTRONICS 2025年 225卷

作者： Kim, Yeeun Jeong, Jaejoong Hong, Seul Ki Cho, Byung Jin Park, Jong Kyung Seoul Natl Univ Sci & Technol Dept Semicond Engn 232 Gongneung Ro Seoul 01811 South Korea Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon 34141 South Korea

This paper addresses the challenge of declining cell current in 3d nand flash memory. We propose a novel approach to deposit a positive fixed oxide charge on the backside adjacent to the filler oxide after forming a polySi channel, effectively improving the cell current flow within the entire string. Through TCAd simulations and experimental device fabrication, we demonstrate a significant enhancement in cell current by approximately 30%. Furthermore, we analyze the impact of positive fixed charge on channel current and investigate the influence of Poly-Si channel thickness and liner oxide thickness on current improvement. Our findings indicate promising avenues for improving 3d nand flash memory technology, contributing to its continued advancement in the future.

关键词： 3d nand flash memory Cell current Poly-Si channel Positive fixed oxide charge

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Optimization of read operation for low power consumption in 3d nand flash memory

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MICROELECTRONIC ENGINEERING 2025年 298卷

作者： Park, Jesun Kim, Seongwoo Cho, Taeyoung Kang, Myounggon Univ Seoul Dept Intelligent Semicond Engn Seoul 02504 South Korea Univ Seoul Sch Adv Fus Studies Seoul 02504 South Korea Korea Natl Univ Transportat Dept Elect Engn Room 326Smart ICT Bldg50 Daehak Ro Chungju Si 27469 Chungbuk South Korea

This study proposes a low power read operation to minimize the hot carrier injection (HCI) phenomenon that occurs during read operations in 3d nand flash memory. Owing to the characteristics of the 3d nand flash memory structure, the channels of unselected strings can easily remain in a floating state. This leads to HCI during read operations, resulting in read disturbances. To improve the read disturb characteristics, triangular pulse voltages (VTP) with adjusted slopes and delayed application times were applied to the string selected line (SSL) and the ground selected line (GSL) during read operations. Using the proposed read scheme, it was confirmed that HCI was decreased compared to the conventional method, and it was possible to operate at low power.

关键词： 3d nand flash memory Channel potential Read disturbance Hot carrier injection (HCI) Channel boosting

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3d nand flash memory with laterally-recessed channel (LRC) and connection gate architecture

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SOLId-STATE ELECTRONICS 2011年第1期55卷 37-43页

作者： Yun, Jang-Gn Lee, Jong duk Park, Byung-Gook Seoul Natl Univ Interuniv Semicond Res Ctr Seoul 151742 South Korea Seoul Natl Univ Sch Elect Engn Seoul 151742 South Korea

A three-dimensional (3d) stacked bit-line nand flash memory is investigated. The fabrication process flow for the formation of a laterally-recessed bit-line stack is described. Program operation is simulated using a stacked bit-line structure. Inter-layer interference (ILI) is addressed and the minimum isolation oxide thickness between stacked bit-lines is extracted. Simple device and array with the laterally-recessed bit-line stack are fabricated and electrical characteristics are measured. A new array architecture having a connection gate is designed for the 3d stacked bit-line nand flash memory application. (C) 2010 Elsevier Ltd. All rights reserved.

关键词： 3d nand flash memory Bit-line stacking Laterally-recessed channel (LRC) Inter-layer interference (ILI) Connection gate scheme array

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3d nand flash memory Cell Current and Interference Characteristics Improvement With Multiple dielectric Spacer

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IEEE ACCESS 2023年 11卷 113704-113711页

作者： Oh, Yun-Jae Lee, Inyoung Suh, Yunejae Kang, daewoong Cho, Il Hwan Myongji Univ Dept Elect Engn Yongin 17058 Gyeonggi Do South Korea Soongsil Univ Dept Elect Engn Seoul 06978 South Korea Seoul Natl Univ Dept Next Generat Semicond Convergence & Open Shar Seoul 08826 South Korea

To achieve high density, the spacer length of three dimensional (3d) nand device has been scaled down. When the program/erase cycle repeats, problems such as electrons accumulation in the inter-cell region are occurred. To solve this problem, a method of replacing the spacer region material of 3d nand device with a low-k materials has been proposed. In 3d nand, carrier's lateral spreading occurs since all cells in the string share a same trap layer. In this work, we observed the change of cell current (I-cell) and interference characteristic after retention time on various dielectric constant of spacer region conditions. These two factors exhibit a trade-off characteristic. In this paper, we suggested the appropriate range of dielectric constant value. Based on this observation, we have proposed a suitable range of dielectric constants and suggested the Si3N4/ Air / Si3N4(N/A/N) multiple dielectric spacer structure to improve both Icell and interference characteristics. In addition, performance improvement can be obtained through high-k / low-k / high-k multiple dielectric spacer structure. Improving the retention characteristics of 3d nand flash memories through the proposed structure will contribute to improving the reliability of memory devices.

关键词： 3d nand flash memory multiple dielectric spacer retention interference electron trap charge lateral migration technology computer aided design (TCAd)

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Impact of Electron and Hole Trap Profiles in BE-TOX on Retention Characteristics of 3d nand flash memory

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2024年 23卷 733-740页

作者： Yoon, Gilsang Go, donghyun Park, Jounghun Kim, donghwi Kim, Jongwoo An, Ukju Kim, Jungsik Lee, Jeong-Soo Kong, Byoung don Pohang Univ Sci & Technol Dept Elect Engn Pohang 37673 South Korea Gyeongsang Natl Univ Dept Elect Engn Jinju 52828 South Korea

Trap profiles in the bandgap-engineered tunneling oxide (BE-TOX) layer of a 3d nand flash memory were investigated using a transient current trap spectroscopy technique. A new pulse scheme was introduced to generate channel holes and subsequently analyze the hole traps in the BE-TOX layer. In the fresh cell, the hole traps were primarily located at a trap energy level (E-T) of 1.1 eV, whereas the electron traps exhibited two distinct peaks at E-T = 0.75 and 1.25 eV. With increasing program/erase (P/E) cycling operations, the peak E-T associated with hole traps shifted toward shallower levels. Conversely, the electron traps remained unchanged, although their intensities increased. The extracted trap generation exhibited the power-law characteristics.

关键词： 3d nand flash memory bandgap-engineered tunneling oxide (BE-TOX) program/erase (P/E) cycling trap profile transient current trap spectroscopy 3d nand flash memory bandgap-engineered tunneling oxide (BE-TOX) program/erase (P/E) cycling trap profile transient current trap spectroscopy

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Adaptive Pulse Programming Scheme for Improving the Vth distribution and Program Performance in 3d nand flash memory

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IEEE JOURNAL OF THE ELECTRON dEVICES SOCIETY 2021年 9卷 102-107页

作者： du, Zhichao Li, Shuang Wang, Yu Fu, Xiang Liu, Fei Wang, Qi Huo, Zongliang Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China Yangtze Memory Technol Co Ltd Wuhan 430205 Peoples R China

For triple-level or quad-level 3d nand flash memory, narrowing the V-th distribution of each state without influencing page program performance is one of the challenges. Considering this challenge, a novel adaptive pulse programming (APP) scheme was proposed. The proposed APP scheme adopted additional verify operations to separate the cells with different programming speed. It enhanced the program effect of slow cells by using increasing programming step voltage, and prevented the fast cells from over programming by using shorter programming pulse width through controlling the voltage of bitline. Compared with general incremental step pulse programming scheme, experimental results on TLC 3d nand flash showed that, APP scheme could reduce the V-th distribution width of cells by around 15% and at the same time save the program time.

关键词： Programming flash memories Sensors Three-dimensional displays Voltage control Microelectronics Licenses 3d nand flash memory ISPP 3-bit per cell Vth distribution

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Investigation of Program Noise in Charge Trap Based 3d nand flash memory

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON dEVICE LETTERS 2020年第1期41卷 30-33页

作者： Hou, Wei Jin, Lei Jia, Xinlei Wang, Zhiyu Wang, Qiguang Luo, Zhe Li, da Xu, Feng Huo, Zongliang Univ Chinese Acad Sci Beijing 100049 Peoples R China Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China Yangtze Memory Technol Co Ltd Wuhan 430205 Hubei Peoples R China

The mechanisms and characteristics of program noise (PN) in charge trap based 3d nand flash memory are investigated in this work. Electron injection statistics is found to be primarily responsible for PN. Moreover, it is found that PN gets worse after program and erase (PE) cycling in 3d charge trapping memory devices. A physical model is proposed to explain the observations. After heavy cycling stress, new traps are generated in the tunnel oxide, and more charges can be trapped. As a result, program speed increases and charge centroid shifts towards the tunnel oxide, which lead to worse PN. Furthermore, the upper part of Vt distribution is broadened after heavy PE cycling. The contribution of the worse PN to the upper part broadening after cycling is studied through Monte Carlo simulation.

关键词： Three-dimensional displays flash memories Electron traps Monte Carlo methods Two dimensional displays Programming Fluctuations 3d nand flash memory program noise cycle Vt distribution Monte Carlo array simulation

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Analysis of Residual Stresses Induced in the Confined 3d nand flash memory Structure for Process Optimization

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IEEE JOURNAL OF THE ELECTRON dEVICES SOCIETY 2022年 10卷 104-108页

作者： Jang, Eun-Kyeong Kim, Ik-Jyae Lee, Cheon An Yoon, Chiweon Lee, Jang-Sik Pohang Univ Sci & Technol Dept Mat Sci & Engn Pohang 37673 South Korea Samsung Elect Co Ltd Flash Design Team Hwasung 18448 South Korea

In flash memory technology, mechanical stress is considered as one of the major factors that can influence the device performance. Furthermore, mechanical stress can have a greater impact on the electrical performance in 3d nand than in 2d nand because 3d nand has a confined structure. Thus, the mechanical stress and its influence on the 3d nand need to be investigated. In this study, we simulated the 3d nand flash to quantify how deposition temperatures of components influenced residual stress and electrical characteristics. The stress distribution and electrical characteristics of the channel were shown to depend on the deposition temperatures of the poly-Si channel, charge trap nitride, tunneling oxide, and tungsten word line in technology computer-aided design simulations. Also, the relationship between residual stress and electrical characteristics was investigated and described using the energy band shift due to residual stress. These results have a potential to improve the cell performances and optimize process parameters in 3d nand flash process technology.

关键词： Stress Tungsten Residual stresses Three-dimensional displays flash memories Solid modeling Transistors 3d nand flash memory mechanical stress deposition temperature device simulation TCAd

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