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IEEE ELECTRON dEVICE LETTERS 2022年第12期43卷 2089-2092页

作者： Lee, Seungmin Choi, Byoungdeog Samsung Elect Co Flash Proc Architecture Team Pyeongtaek 17786 South Korea Sungkyunkwan Univ Dept Semicond & Display Engn Suwon 16419 South Korea Sungkyunkwan Univ Dept Elect & Comp Engn Suwon 16419 South Korea

This letter proposes a novel capacitor-less dynamic random-accessmemorycomposed of a 3dstacked cell array. To perform selective program and erase operations in the 3d cell array, a back-gate-sharing and channel-separating architecture are adopted. The operation of the unit cell is demonstrated through 3d technology computer-aided design simulations. The proposed device uses a simple process to optimize the back gate (e.g., modifying the thickness ofmaterials or using different types of materials). Through optimization of the back gate, a sensing margin and retention time of 52 mu A and 475 ms, respectively, are achieved at 300 K in a scaled cell with a gate length of 30 nm and channel radius of 30 nm. Because this device has a cell array similar to that of a 3d nand flash memory, it can be manufactured using the same process and equipment in a cost-effective manner. In addition, it can be adopted in processing- in-memory applications to provide high-performance and high-density hybridmemory functionalitywhen used in conjunction with nand flash memories. Index

关键词： Random access memory Three-dimensional displays Logic gates Silicon Computer architecture Sensors flash memories 3d dRAM 3d nand flash memory capacitor-less dRAM embedded memory processing-in-memory stacking

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A Novel Program Scheme for Program disturbance Optimization in 3-d nand flashmemory

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON dEVICE LETTERS 2018年第7期39卷 959-962页

作者： Zhang, Yu Jin, Lei Zou, Xingqi Liu, Hongtao Zhang, An Huo, Zongliang Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China Univ Chinese Acad Sci Sch Microelect Beijing 100049 Peoples R China Univ Chinese Acad Sci Beijing 100049 Peoples R China Yangtze Memory Technol Co Ltd Wuhan 430205 Hubei Peoples R China

A new program scheme using an "eraselike" waveform for precharge operation is proposed for program disturbance optimization in 3-d vertical channel flash memories. With the proposed scheme, the effect of precharge operation, which is followed by program operation, on the initial unselected channel is enhanced by charging additional holes from p-type well. Consequently, boosting efficiency and boosting potential of unselected string are promoted, leading to a significant suppressed programdisturbance, and the V-pass windowcan be enlarged notably as well. Meanwhile, the timing requirement of the proposed scheme is evaluated. The advantage of the erase assisted precharge scheme has been demonstrated by TCAd simulation and measurement in mini-array test-key device.

关键词： 3d nand flash memory vertical poly silicon channel erase assisted precharge program scheme program disturbance

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An Efficient dynamic Threshold Voltage detection Scheme for Improving 3-d nand flash Reliability

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IEEE TRANSACTIONS ON dEVICE ANd MATERIALS RELIABILITY 2024年第4期24卷 529-543页

作者： Yin, Linxin Li, Yingzhao Zhang, Xiaoyi Zhai, Xiongfei Han, Guojun Guangdong Univ Technol Sch Informat Engn Guangzhou 510006 Peoples R China

With high storage density and large capacity, three-dimensional (3d) nand flash utilizing multi-level storage technology has become the mainstream storage medium. Furthermore, by storing multiple bits in each flash cell, 3d nand flash memory can achieve much larger storage capacity. However, the threshold voltage distribution in 3d nand flash memory tends to shift after repeated program/erase and long retention time, leading to more detection error when adopting conventional fixed read reference voltage (RRV). To address this issue, in this work we investigate error characteristics of 3d floating-gate (FG) and charge-trap (CT) nand flash memory, including the reliability variations of different layers and pages, and threshold voltage shifting. We propose an efficient dynamic threshold voltage detection (EdTVd) scheme by exploiting the error characteristics and the features of the data writing process of nand flash to optimize RRV. Based on the Nanocycler test platform, the test results show that our proposed scheme can significantly reduce raw bit error rates (RBER) during reading processes and the step count is relatively low. The RBER of the EdTVd scheme is almost equal to the optimal read scheme, and the number of step count is close to 3 fixed-step read scheme.

关键词： flash memories Three-dimensional displays Threshold voltage Reliability memory management Microprocessors decoding 3d nand flash memory EdTVd retention time P/E cycles RBER

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Impact of Grain Length and Grain Boundary on dispersion of Threshold Voltage for 3-dimensional Gate-All-Around Polysilicon Channel memory

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JOURNAL OF NANOSCIENCE ANd NANOTECHNOLOGY 2017年第12期17卷 9257-9261页

作者： Kim, Kyu-Beom Oh, Young-Taek Song, Yun-Heub Hanyang Univ Dept Elect Engn Seoul 04763 South Korea

Using simulations, we investigated the impact of grain physical parameters in a poly-silicon channel on the dispersion of cell threshold voltages in a gate-all-around channel structure, which is used in 3-dimensional nand flash memory. Here, cell characteristics were evaluated for various grain length (L-G) and grain boundary trap density (N-GB) values. The dispersion of the threshold voltages was investigated as a function of these parameters in a string with 12 cells. We confirmed that a shorter grain length and higher grain boundary trap density in a poly-silicon vertical channel resulted in poor cell characteristics, namely a lower cell current and a less favorable sub-threshold slope. In addition, we showed that the variations in cell characteristics in a string significantly increased with decreasing grain length and increased trap density in the poly-silicon channel. From these results, we expect that increasing the grain length and minimizing the grain boundary trap density are important methods of decreasing the dispersion of the cell threshold voltages in a string.

关键词： 3d nand flash memory Threshold Voltage distribution Polysilicon Channel Grain Grain Boundary Trap

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Multi-Level Threshold Voltage Setting Method of String Select Transistors for Layer Selection in Channel Stacked nand flash memory

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON dEVICE LETTERS 2015年第12期36卷 1318-1320页

作者： Kwon, dae Woong Kim, Wandong Kim, do-Bin Lee, Sang-Ho Seo, Joo Yun Baek, Myung Hyun Park, Ji-Ho Choi, Eunseok Cho, Gyu Seong Park, Sung-Kye Park, Byung-Gook Seoul Natl Univ Dept Elect Engn & Comp Sci Interuniv Semicond Res Ctr Seoul 151744 South Korea SK Hynix Inc Div Res & Dev Inchon 467734 South Korea

In this letter, we propose a simplified channel-stacked array with a layer selection by multi-level operation (SLSM) and a new string select transistors (SSTs) threshold voltage (V-th) setting method that all the SSTs on each layer are set to targeted the V-th values simultaneously by one erase operation. To verify the validity of the new method in SLSM, TCAd simulations are performed, and a fabricated pseudo SLSM is measured. It is verified that the V-th values of SSTs are set to the targeted V-th values by the new method. Moreover, memory operations are examined in the fabricated structure after setting the V-th values of all the SSTs by the new method. As a result, stable memory operations are obtained successfully without the interference between stacked layers.

关键词： 3d nand flash memory channel stacked nand flash memory stacked layer selection LSM SST threshold voltage setting

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Implementation of data Search in Multi-Level nand flash memory by Complementary Storage Scheme

IEEE ELECTRON DEVICE LETTERS

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IEEE ELECTRON dEVICE LETTERS 2020年第8期41卷 1189-1192页

作者： Wang, Fei Feng, Yang Zhan, Xuepeng Chen, Bing Chen, Jiezhi Shandong Univ Sch Informat Sci & Engn Qingdao 266100 Peoples R China Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou 310027 Peoples R China

We develop a novel scheme to realize data search in nand flash memories, which is important for a wide variety of applications in data centers. In our design, the pair unit consists of double neighbor cells in the nand string, one "data cell" and one "complementary cell". The nand string will be at the "Pass" state only when the searching data are completely matched with the stored data. Parameters that affect data search performance are analyzed systematically. Based on simulations in vertically stacked 3d nand structures, it is shown that the bit-line current ratio of the fully matched case to the worst case of one mismatched data is more than similar to 10(4) in both MLC (multi-level cell) and TLC (triple-level cell) modes, and similar to 10(2) can still be obtained in QLC (quad-level cell) mode after read voltage optimizations. These results indicate that the proposed scheme is effective for data search in multi-level nand flash memories and also friendly for peripheral circuits design.

关键词： 3d nand flash memory complementary storage data search simulations

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Cross-Temperature Reliability of 3d nand: Cell-to-Cell Variability Analysis and Countermeasure

Cross-Temperature Reliability of 3D NAND: Cell-to-Cell Varia...

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International Reliability Physics Symposium (IRPS)

作者： Kumar, Mondol Anik Ray, Biswajit Colorado State Univ Elect & Comp Engn Dept Ft Collins CO 80523 USA

ISBN: (纸本)9798350369762;9798350369779

Cross-temperature effect is a significant reliability concern for 3d nand flash memory. In this paper we explore the origin of cross-temperature reliability by measuring the cell threshold voltage (v(th)) distribution at different temperatures. We observe significant cell- to-cell variability in the temperature coefficients causing distribution widening. We provide a conceptual picture to understand the distribution widening based on sub-threshold slope factor variation. We also discuss two system level countermeasures to minimize the cross-temperature effects.

关键词： 3d nand flash memory Cross Temperature Variability

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Study of Trap Generation in nand flash Tunnel Oxide using TCAd 8

Study of Trap Generation in NAND Flash Tunnel Oxide using TC...

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8th Electron devices Technology & Manufacturing Conference (EdTM)

作者： Kumar, Anuj Tiwari, Ravi Bajaj, Mohit dolgos, denis Smith, Lee Mahapatra, Souvik Indian Inst Technol Dept Elect Engn Mumbai 400076 Maharashtra India Synopsys India Pvt Ltd Bangalore Karnataka India Synopsys LLC Zurich Switzerland Synopsys Inc Mountain View CA USA

ISBN: (纸本)9798350383089;9798350371529

The Physical TCAd models, which have been validated for the aging of logic devices, are utilized to simulate trap generation (TG) in a memory device during program/erase (P/E) cycling. The models are similar to ones describing Positive Bias Temperature Instability (PBTI) for Program and Negative Bias Temperature Instability (NBTI) for Erase. A generic Reaction-diffusion-drift (Rdd) model is used to simulate trap generation in the tunnel oxide of 3d nand flash memory cells during P/E cycling. The impact of cycling for different P/E bias conditions and bake temperatures have been explored using a two-dimensional (2d) cross-section of a 3d nand flash memory string.

关键词： Reaction-diffusion-drift Model 3d nand flash memory Tunnel Oxide degradation trap-generation Program Erase cycling

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Angstrom-accuracy multilayer thickness determination using optical metrology and machine learning 12

Angstrom-accuracy multilayer thickness determination using o...

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Conference on Optical Measurement Systems for Industrial Inspection XII

作者： Kwak, HyunSoo Ryu, Sungyoon Cho, Suil Kim, Junmo Yang, Yusin Kim, Jungwon Korea Adv Inst Sci & Technol KAIST Dept Mech Engn Daejeon 34141 South Korea Samsung Elect Co Ltd Memory Mfg Technol Ctr Memory Metrol & Inspect Technol Team Gyeonggi Do 18448 South Korea Korea Adv Inst Sci & Technol KAIST Sch Elect Engn Daejeon 34141 South Korea

ISBN: (数字)9781510643994

ISBN: (纸本)9781510643994

The era of big data and cloud computing services has driven the demand for higher capacity and more compact semiconductor devices. As a result, semiconductor devices are moving from 2-d to 3-d. Most notably, three-dimensional (3d) nand flash memory is the most successful 3d semiconductor device today. 3d nand overcomes the spatial limitation of conventional planar nand by stacking memory cells vertically. Since hundreds of vertically stacked semiconductor materials become the channel length in the final product, accurate thickness characterization is critical. In this paper, we propose a non-destructive multilayer thickness characterization method using optical measurements and machine learning. For a silicon oxide/nitride multilayer stack of >200 layers, we could predict the thickness of each layer with an average root-mean-square error (RMSE) of 1.6 angstrom. In addition, we could successfully classify normal and outlier devices using simulated data. We expect this method to be highly suitable for semiconductor fabrication processes.

关键词： 3d nand flash memory Multilayer thickness characterization Ellipsometry Group delay dispersion Machine learning

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Evanesco: Architectural Support for Efficient data Sanitization in Modern flash-Based Storage Systems 20

Evanesco: Architectural Support for Efficient Data Sanitizat...

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25th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Kim, Myungsuk Park, Jisung Cho, Geonhee Kim, Yoona Orosa, Lois Mutlu, Onur Kim, Jihong Seoul Natl Univ Seoul South Korea Swiss Fed Inst Technol Zurich Switzerland

ISBN: (纸本)9781450371025

As data privacy and security rapidly become key requirements, securely erasing data from a storage system becomes as important as reliably storing data in the system. Unfortunately, in modern flash-based storage systems, it is challenging to irrecoverably erase (i.e., sanitize) a file without large performance or reliability penalties. In this paper, we propose Evanesco, a new data sanitization technique specifically designed for high-density 3d nand flash memory. Unlike existing techniques that physically destroy stored data, Evanesco provides data sanitization by blocking access to stored data. By exploiting existing spare flash cells in the flash memory chip, Evanesco efficiently supports two new flash lock commands (pLock and block) that disable access to deleted data at both page and block granularities. Since the locked page (or block) can be unlocked only after its data is erased, Evanesco provides a strong security guarantee even against an advanced threat model. To evaluate our technique, we build SecureSSd, an Evanesco-enabled emulated flash storage system. Our experimental results show that SecureSSd can effectively support data sanitization with a small performance overhead and no reliability degradation.

关键词： solid-state drives (SSds) 3d nand flash memory security privacy data sanitization

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