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3d integration technology for lab-on-a-chip applications

ELECTRONICS LETTERS 2011年第26期47卷 S22-S24页

作者： Temiz, Y. Kilchenmann, S. Leblebici, Y. Guiducci, C. Ecole Polytech Fed Lausanne Lab Life Sci Elect CLSE CH-1015 Lausanne Switzerland Ecole Polytech Fed Lausanne LSM CH-1015 Lausanne Switzerland

A review is presented of advances and challenges in fully integrated systems for personalised medicine applications. One key issue for the commercialisation of such systems is the disposability of the assay-substrate at a low cost. This work adds a new dimension to the integrated circuits technology for lab-on-a-chip systems by employing 3d integration for improved performance and functionality. It is proposed that a disposable biosensing layer can be aligned and temporarily attached to the 3d CMOS stack by the vertical interconnections, and can be replaced after each measurement.

关键词： 3d CMOS stack 3d integration technology assay-substrate biomedical electronics commercialisation disposability disposable biosensing layer fully integrated systems integrated circuit interconnections integrated circuits technology lab-on-a-chip lab-on-a-chip applications personalised medicine applications vertical interconnections

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Extraction of Equivalent High Frequency Models for TSV and RdL Interconnects Embedded in Stacks of the 3d integration technology

Extraction of Equivalent High Frequency Models for TSV and R...

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15th IEEE Workshop on Signal Propagation on Interconnects (SPI)

作者： Fourneaud, L. Lacrevaz, T. Charbonnier, J. Fuchs, C. Farcy, A. Bermond, C. Eid, E. Roullard, J. Flechet, B. Univ Savoie IMEP LAHC CNRS UMR 5130 F-73376 Le Bourget Du Lac France CEA LETI Minatec F-38054 Grenoble 9 France STMicroelectronics F-38926 Crolles France

ISBN: (纸本)9781457704673

Interconnections such as Through Silicon Via (TSV) and Redistribution Layer (RdL) constitute one of key components to acquire high performance in 3d integrated circuits. These interconnections deal with an unusual environment as they are embedded in silicon substrates which could modify largely their propagation properties. In addition architectures of TSV and BRdL are complex in terms of design and stack of materials. Thus, it is essential to characterize them in high frequency in order to analyze, predict and optimize their performance. In this paper, we present results of TSV and BRdL electrical models extractions up to 20 GHz obtained by taking advantage of an innovative de-embedding method using silicon photoconductive properties.

关键词： 3d integrated circuits 3d integration technology BRdL electrical models Impedance Integrated circuit interconnections RdL interconnects Si Silicon Substrates TSV interconnects Three dimensional displays Through-silicon vias Transmission line matrix methods elemental semiconductors equivalent high-frequency models innovative deembedding method integrated circuit interconnections integrated circuit modelling redistribution layer silicon silicon photoconductive properties silicon substrates substrates three-dimensional integrated circuits through silicon via

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A New Thermomechanical Fracture Analysis Approach for 3d integration technology

A New Thermomechanical Fracture Analysis Approach for 3D Int...

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IEEE 61st Electronic Components and technology Conference (ECTC)

作者： Agwai, Abigail Guven, Ibrahim Madenci, Erdogan Univ Arizona Dept Aerosp & Mech Engn Tucson AZ 85721 USA

ISBN: (纸本)9781612844985

In this study, the peridynamic framework is applied to model heat diffusion to derive peridynamic heat diffusion equations. A numerical scheme is put forward and implemented in order to establish the validity of these equations. Finally, an approach is developed for coupled solution of heat conduction and solid mechanics equations in the realm of peridynamics.

关键词： 3d integration technology Equations Finite element methods Heating Mathematical model Solids Steady-state coupled solution heat conduction heat conduction integrated circuit packaging peridynamic framework peridynamic heat diffusion equations solid mechanics equations thermomechanical fracture analysis approach three-dimensional integrated circuits

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Optimization-based Reconfigurable Approach for Low-Power 3d Chip-multiprocessors 9

Optimization-based Reconfigurable Approach for Low-Power 3D ...

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9th IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： dorostkar, Aniseh Asad, Arghavan Fathy, Mahmood Mohammadi, Farah Iran Univ Sci & Technol Comp Engn Dept Tehran Iran Ryerson Univ Elect & Comp Engn Dept Toronto ON Canada

ISBN: (纸本)9781538623114

Future dark silicon chip-multiprocessors (CMPs) consist of many cores and uncores where only a few of them can be simultaneously powered on or utilized within the peak power. In this paper, we present a run-time convex optimization to reconfigure hybrid cache hierarchy and 3d NoC based CMP to minimize the power consumption and improves chip performance. The proposed approach dynamically estimate the read and write frequency of memory banks for next time interval and reconfigure the 3d chip by darkening or activating the dRAM/STT-RAM banks and TSV. Experimental result on PARSEC benchmark shows that the runtime reconfigurable approach improves the power consumption by about 39% on average.

关键词： 3d integration technology dark silicon Non-Volatile Memory (NVM) Reconfigurable cache Run-time optimization problem Through-Silicon-Vias (TSV)

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Three-dimensional integration technology Using Through-Si Via Based on Reconfigured Wafer-to-Wafer Bonding

Three-Dimensional Integration Technology Using Through-Si Vi...

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32nd Annual Custom Integrated Circuits Conference CICC

作者： Koyanagi, Mitsumasa Fukushima, Takafumi Tanaka, Tetsu Tohoku Univ New Ind Creat Hatchery Ctr NICHe Sendai Miyagi 9808579 Japan Tohoku Univ Grad Sch Biomed Engn Sendai Miyagi 9808579 Japan

ISBN: (纸本)9781424457601

Three-dimensional (3-d) integration technologies using through-silicon vias (TSV's) are described. We have developed a 3-d integration technology using TSV's based on a wafer-to-wafer bonding method for the fabrication of new 3-d LSIs. A 3-d image sensor chip, 3-d shared memory chip, 3-d artificial retina chip and 3-d microprocessor test chip have been fabricated by using this technology. In addition, we have developed a new 3-d integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration. A number of known good dies (KGds) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip integration.

关键词： 3d artificial retina chip 3d image sensor chip 3d integration technology 3d microprocessor test chip 3d shared memory chip known good dies large scale integration large scale integration microprocessor chips reconfigured wafer-to-wafer bonding self-assembly self-assembly technique shared memory systems super-chip integration three-dimensional integrated circuits through-silicon vias wafer bonding

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Layer-Aware design Partitioning for Vertical Interconnect Minimization

Layer-Aware Design Partitioning for Vertical Interconnect Mi...

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IEEE-Computer-Society Annual Symposium on VLSI (ISVLSI)

作者： Huang, Ya-Shih Liu, Yang-Hsiang Huang, Juinn-dar Natl Chiao Tung Univ Dept Elect Engn Hsinchu 30010 Taiwan Natl Chiao Tung Univ Inst Elect Hsinchu 30010 Taiwan

ISBN: (纸本)9780769544472

Three-dimensional (3d) design technology, which has potential to significantly improve design performance and ease heterogeneous system integration, has been extensively discussed in recent years. This emerging technology allows stacking multiple layers of dies and typically resolves the vertical inter-layer connection issue by through-silicon vias (TSVs). However, TSVs also occupy significant silicon estate as well as incur reliability problems. Therefore, the deployment of TSVs must be very judicious in 3d designs. In this paper, we propose an iterative layer-aware partitioning algorithm, named iLap, for TSV minimization in 3d structures. iLap iteratively applies multi-way min-cut partitioning to gradually divide a given design layer by layer in the bottom-up fashion. Meanwhile, iLap also properly fulfills a specific I/O pad constraint incurred by 3d structures to further improve its outcome. Experimental results show that iLap can reduce the number of TSVs by about 35% as compared to several existing state-of-the-art methods. We believe a good TSV-minimized 3d partitioning solution can serve as a good starting point for further tradeoff operations between TSV count and wirelength.

关键词： through-silicon via (TSV) 3d integration technology layering partitioning

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Study on a kind of thermal source chip for the performance analysis of micro channel heat sink: simulation and experimental validation 22

Study on a kind of thermal source chip for the performance a...

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22nd International Conference on Electronic Packaging technology (ICEPT)

作者： Zhao, Ming Zhang, Jian Lu, Qian Xiang, Weiwei Li, Yangyang Jiang, Miaomiao Ye, Huijie Peng, Ting Southwest China Res Inst Elect Equipment Chengdu Peoples R China

ISBN: (纸本)9781665413916

Micro channel cooling technology is one kind of forced heat exchange cooling technology, and has good potential applications in high power electronic devices and microsystem integration field. However, the performance analysis is a technical issue for the application of micro channel heat sink. A thermal source chip for analyzing the performance of micro channel heat sink accurately and conveniently is presented in this paper. In order to analyze the performance of thermal source chip, the thermodynamics simulation is carried out by using finite element software. Then, the thermal source chip is fabricated, and the thermal measuring experiment is performed to verify the simulation results. The simulation results indicate that the surface temperature of thermal source chip increases with the applied voltage, and the maximum heat flux of thermal source chip appeared at the 80 V applied voltage. The experiment results show good agreement with the simulation.

关键词： 3d integration technology Micro channel cooling technology thermal source chip

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Electrical Characterization and Impact on Signal Integrity of New Basic Interconnection Elements inside 3d Integrated Circuits

Electrical Characterization and Impact on Signal Integrity o...

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IEEE 61st Electronic Components and technology Conference (ECTC)

作者： Roullard, J. Capraro, S. Farcy, A. Lacrevaz, T. Bermond, C. Leduc, P. Charbonnier, J. Ferrandon, C. Fuchs, C. Flechet, B. Univ Savoie IMEP LAHC UMR CNRS 5130 F-73376 Le Bourget Du Lac France STMicroelect F-38926 Crolles France CEA LETI Minate F-38054 Grenoble 9 France

ISBN: (纸本)9781612844985

developments in 3d integration technology reveal several basic interconnect elements, as Through Silicon Via, Redistribution Layers, Cu-Pillar and bumps to transmit signals inside 3d circuits. Impact of the interconnect elements on high speed signal integrity all along the global 3d interconnection chain requires investigation. First each element was successively characterized and an equivalent electrical model was extracted in the frequency domain from measurements or simulations. Next these models were realistically chained to simulate the signal integrity performance, declined as delay, of the global 3d-IC interconnection chain in order to determine the best strategies among the multitude of options involved in 3d integration. Three studies were investigated in detail regarding routing strategy, the choice of chip stack orientations (Face-to-Face or Face-to-Back), and the comparison of various 3d technologies available, resulting in global recommendations for future 3d products.

关键词： 3d integrated circuit 3d integration technology delay Frequency measurement Integrated circuit interconnections Routing Three dimensional displays Through-silicon vias Transmission line measurements chip stack electric fields electrical characterization electrical model frequency domain frequency-domain analysis global 3d-IC interconnection chain high speed signal integrity integrated circuit interconnections integrated circuit modelling interconnection elements network routing pillar-and-bumps redistribution layer routing strategy three-dimensional integrated circuits through silicon via

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Heterogeneous die Stacking of SRAM Row Cache and 3-d dRAM: An Empirical design Evaluation

Heterogeneous Die Stacking of SRAM Row Cache and 3-D DRAM: A...

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54th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Woo, dong Hyuk Seong, Nak Hee Lee, Hsien-Hsin S. Intel Labs Santa Clara CA 95054 USA

ISBN: (纸本)9781612848570

As dRAM scaling becomes more challenging and its energy efficiency receives a growing concern for data center operation, an alternative approach-stacking dRAM die with thru-silicon vias (TSV) using 3-d integration technology is being undertaken by industry to address these looming issues. Furthemore, 3-d technology also enables heterogeneous die stacking within one dRAM package. In this paper, we study how to design such a heterogeneous dRAM chip for improving both performance and energy efficiency, in particular, we propose a novel floorplan and several architectural techniques to fully exploit the benefits of 3-d die stacking technology when integrating an SRAM row cache into a dRAM chip. Our multi-core simulation results show that, by tightly integrating a small row cache with its corresponding dRAM array, we can improve performance by 30% while saving dynamic energy by 31% for memory intensive applications.

关键词： 3d dRAM 3d die stacking technology 3d integration technology dRAM array dRAM chips Educational institutions Lead SdRAM SRAM chips SRAM row cache TSV Through-silicon vias empirical design evaluation energy efficiency heterogeneous die stacking integrated circuit packaging multicore simulation three-dimensional integrated circuits thru-silicon vias

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development of a Three-dimensional Integrated Image Sensor with Pixel-Parallel Signal Processing Architecture 14

Development of a Three-Dimensional Integrated Image Sensor w...

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2015 IEEE SENSORS

作者： Hagiwara, Kei Goto, Masahide Honda, Yuki Nanba, Masakazu Ohtake, Hiroshi Iguchi, Yoshinori Saraya, Takuya Kobayashi, Masaharu Toshiyoshi, Hiroshi Higurashi, Eiji Hiramoto, Toshiro NHK Japan Broadcasting Corp Sci & Technol Res Labs Tokyo Japan Univ Tokyo Tokyo Japan

ISBN: (纸本)9781479982035

A prototype sensor was built to demonstrate a 3d integrated CMOS image sensor that incorporates pixel-parallel signal processing architecture. FdSOI substrates with photodiodes and in-pixel AdC circuits were directly bonded after surface activation by plasma treatment. X, Y and theta alignment errors of 20 bonded samples were reduced to within +/- 0.7 mu m, +/- 0.4 mu m, and +/- 0.004 degrees, respectively by using IR camera system. The resulting sensor successfully captured video images, thus demonstrating the feasibility of 3d integration technology and pixel-parallel architecture for future CMOS image sensors.

关键词： 3d integration technology CMOS image sensor wafer bonding

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