The securityprocessor proposed in this paper is composed by multiple cryptographic cores. And due to the use of embedded DMA and data burst transfer, the processor can act as a bus master. This architecture improves ...
详细信息
The securityprocessor proposed in this paper is composed by multiple cryptographic cores. And due to the use of embedded DMA and data burst transfer, the processor can act as a bus master. This architecture improves the efficiency of system bus and reduces the burden of host CPU. Additionally, the proposed processor is connected to the system bus via a galswrapper. Thus, high throughput can be achieved by using faster clock than the host CPU utilizes. On the other hand, the clock of the securityprocessor can also be slowed down if the low power application is desired.
The securityprocessor proposed in this paper is composed by multiple cryptographic *** due to the use of embedded DMA and data burst transfer,the processor can act as a bus *** architecture improves the efficiency of...
详细信息
The securityprocessor proposed in this paper is composed by multiple cryptographic *** due to the use of embedded DMA and data burst transfer,the processor can act as a bus *** architecture improves the efficiency of system bus and reduces the burden of host ***,the proposed processor is connected to the system bus via a gals ***, high throughput can be achieved by using faster clock than the host CPU *** the other hand,the clock of the securityprocessor can also be slowed down if the low power application is desired.
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