This paper presentsThis paper presents an advanced1dinterpolationarchitecture for avs video coding *** approaches have demerit of low data *** proposeddesign parallel filters the horizontal data andserial filters...
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This paper presentsThis paper presents an advanced1dinterpolationarchitecture for avs video coding *** approaches have demerit of low data *** proposeddesign parallel filters the horizontal data andserial filters the vertical data,thus greatly improve the *** result shows it outperforms conventional designs in processing cycle and chip *** prototype design costs 26.2K gates when synthesized at 108MHz using 0.18 μm CMOS *** This paper presents an advanced1dinterpolationarchitecture for avs video coding *** approaches have demerit of low data *** proposeddesign parallel filters the horizontal data andserial filters the vertical data,thus greatly improve the *** result shows it outperforms conventional designs in processing cycle and chip *** prototype design costs 26.2K gates when synthesized at 108MHz using 0.18 μm CMOS technology. an advanced1dinterpolationarchitecture for avs video coding *** approaches have demerit of low data *** proposeddesign parallel filters the horizontal data andserial filters the vertical data,thus greatly improve the *** result shows it outperforms conventional designs in processing cycle and chip *** prototype design costs 26.2K gates when synthesized at 108MHz using 0.18 μm CMOS technology.
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