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AdapTracer:Adaptive path profiling using arithmetic coding

JOURNAL OF SYSTEMS ARCHITECTURE 2018年 88卷 74-86页

作者： Chen, Gonglong Dong, Wei Zhejiang Univ Coll Comp Sci Hangzhou Zhejiang Peoples R China

Path profiling, which aims to trace the execution path of programs, has been widely adopted in various areas such as record and replay, program optimizations, performance diagnosis and etc. Many path profiling approaches have been proposed in the literature, including the BLPP (Ball-Larus Path Profiling) algorithm, and PAP (Profiling All Path). Unfortunately, both approaches suffer from large tracing overhead for representing long execution paths. In this paper, we propose AdapTracer, a path profiling approach based on arithmetic coding. There are two salient features in AdapTracer. First, it is space efficient by adopting a path profiling algorithm based on arithmetic coding. Second, it is adaptive by explicitly considering the execution frequency of each edge. We have implemented AdapTracer to profile Android applications. Our experimental evaluation uses modified JGF benchmarks to show AdapTracer's efficiency. Experimental results show that AdapTracer reduces the trace size by 44% on average and incurs execution overhead by 10% at most compared to PAP.

关键词： Path profiling arithmetic coding Adaptive tracing

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Finite-precision arithmetic coding via index-splitting and probability-fitting

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APPLIED MATHEMATICS AND COMPUTATION 2005年第2期167卷 976-995页

作者： Chan, DY Ku, CY Natl Chiayi Univ Dept Comp Sci & Informat Engn Chiayi Taiwan Natl Chung Cheng Univ Dept Informat Management Chiayi Taiwan

This paper proposes a fitting-by-splitting algorithm (abbreviated as the FS algorithm), which is composed of an index-splitting (IS) algorithm and a probability-fitting (PF) algorithm, to effectively achieve the finite-precision arithmetic coding code named as the FS-AC code. The FS algorithm generates the FS-AC codes of arbitrarily specified length without the need of post-appended sentinel symbol or pre-affixed side-information bits. Its IS process can split the input symbols into paired indices to make the residual information space be reused as effectively as possible at the end of arithmetically encoding a fixed-precision code. And, the PF process performs after each IS operation for enhancing the reuse efficiency via a fast adaptation process of probability table. Through the integration of IS and PF processes, not only the coding efficiency of proposed finite-precision AC codec can be close to that of unlimited precision AC codec especially for our proposed binary AC codecs. And also, consecutive FS-AC codes can be mutually independent such that the error propagation can be almost blocked to an AC code in problem. Hence, our new AC codecs can be appropriate for generating finite-precision AC codes in the high-speed networks. (c) 2004 Elsevier Inc. All rights reserved.

关键词： arithmetic coding binary arithmetic coding index-splitting

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An Effective Error Correction Scheme for arithmetic coding

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MATHEMATICAL PROBLEMS IN ENGINEERING 2015年第1期2015卷 1-10页

作者： Lin, Qiuzhen Wong, Kwok-Wo Li, Ming Chen, Jianyong Shenzhen Univ Coll Comp Sci & Software Engn Shenzhen 518060 Peoples R China City Univ Hong Kong Dept Elect Engn Kowloon 999077 Hong Kong Peoples R China E China Normal Univ Shanghai Key Lab Multidimens Informat Proc Shanghai 200241 Peoples R China E China Normal Univ Sch Informat Sci & Technol Shanghai 200241 Peoples R China

We propose an effective error correction technique for arithmetic coding with forbidden symbol. By predicting the occurrence of the subsequent forbidden symbols, the forbidden region is actually expanded and theoretically, a better error correction performance can be achieved. Moreover, a generalized stack algorithm is exploited to detect the forbidden symbol beforehand. The proposed approach is combined with the maximum a posteriori (MAP) metric to keep the highly probable decoding paths in the stack. Simulation results justify that our scheme performs better than the existing MAP methods on the error correction performance, especially at a low coding rate.

关键词： ERROR correction (Information theory) arithmetic coding PERFORMANCE evaluation FUNCTIONS (Mathematics) MATHEMATICAL analysis

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Approximate arithmetic coding for bus transition reduction in low power designs

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2005年第6期13卷 696-707页

作者： Lekatsas, H Henkel, J Wolf, W NEC Labs Amer Inc Princeton NJ 08540 USA Univ Karlsruhe D-76128 Karlsruhe Germany Princeton Univ Dept Elect Engn Princeton NJ 08540 USA

We present a method for reducing the power consumption of compressed-code systems by selectively inverting bits that are transmitted on the bus. By incorporating bus inversion into code compression/decompression, we reduce power consumption with no cost in hardware or power relative to code compression without inversion. Inverting has to be done carefully to ensure that the codes can still be decoded. As an additional challenge, compression will generally increase bit-toggling as it removes redundancies from the code transmitted. Therefore, we need to find the right balance between compression ratio and bit-toggling reduction. This paper presents a suitable algorithm that will combine approximate compression techniques with bit-toggling reduction and will explore the various tradeoffs. We take advantage of the approximations introduced to modify codes and reduce bit-toggling, while maintaining compression performance and decoding speed. An interesting result that is derived from our work is that high compression ratios do not necessarily result in the lowest power consumption. By using our method, bus-related power consumption has been reduced by as much as 35% compared to a system with no compression, and as much as 14% compared to a compressed-code system. Bit-toggling reduction does not impose any additional hardware costs other than the decompression engine. We also present a detailed analysis on how bus widths affect bit-toggling when transmitting compressed code, and we show experimental results on ARM, MIPS, and SPARC code. We finally compare our work with Bus Invert and show results that are superior except for the random data case where Bus Invert performs better.

关键词： arithmetic coding code compression low power design

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A pipeline chip for Quasi arithmetic coding

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2001年第4期E84A卷 1034-1041页

作者： Wiseman, Y Bar Ilan Univ Dept Math & Comp Sci IL-52900 Ramat Gan Israel Jerusalem Coll Technol Dept Comp Engn IL-91160 Jerusalem Israel

A combination of a software and a systolic hardware implementation for the Quasi arithmetic compression algorithm is presented. The hardware is implemented as a pipeline hardware implementation. The implementation doesn't change the the algorithm. It just split it into two parts. The combination of parallel software and pipeline hardware can give very fast compression without decline of tile compression efficiency.

关键词： pipeline structure compression arithmetic coding hardware-software combination

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Novel design of arithmetic coding for data compression

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1995年第6期142卷 419-424页

作者： Jiang, J Dept. of Comput. Sci. Loughborough Univ. of Technol. UK

The paper presents a novel software and hardware design of a universal arithmetic coding algorithm where 256 ASCII codes of symbols, as a specific example, are in the alphabet. Essentially. the two coding equations are modified by specifying the code values as the lower end-point value of the coding range and the width of this range. Therefore the procedures of sending output codes, solving the so-called underflow problem, and updating the coding range can be unified and simply controlled by the value of the coding range. As a result, a hardware architecture can be directly designed to implement the algorithm on real-time basis where the single operation of normalisation can be implemented in parallel. In addition, specific design of decoding the compressed output, theoretical analysis and realtime architectures of both encoding and decoding are described. Practical C source codes of main functions and experimental results are also reported.

关键词： arithmetic coding data compression algorithm design signal processing

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An FFGA-based implementation of multi-alphabet arithmetic coding

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2007年第8期54卷 1678-1686页

作者： Mahapatra, Sudipta Singh, Kuldeep Indian Inst Technol Dept Elect & Elect Commun Kharagpur 721302 W Bengal India

A fully parallel implementation of the multi-alphabet arithmetic-coding algorithm, an integral part of many lossless data compression systems, had so far eluded the research community. Although schemes were in existence for performing the encoding operation in parallel, the data dependencies involved in the decoding phase prevented its parallel execution. This paper presents a scheme for the parallel-pipelined implementation of both the phases of the arithmetic-coding algorithm for multisymbol alphabets in high-speed programmable hardware. The compression performance of the proposed scheme has been evaluated and compared with an existing sequential implementation in terms of average compression ratio as well as the estimated execution time for the Canterbury Corpus test set of files. The proposed scheme facilitates hardware realization of both coder and decoder modules by reducing the storage capacity necessary for maintaining the modeling information. The design has been synthesized for Xilinx field-programmable gate arrays and the synthesis results obtained are encouraging, paving the way for further research in this direction.

关键词： arithmetic coding decoding higher order context models lossless data compression parallel architectures

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PARALLEL DESIGN OF arithmetic coding

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1994年第6期141卷 327-333页

作者： JIANG, J JONES, S LOUGHBOROUGH UNIV TECHNOL DEPT ELECTR & ELECT ENGNLOUGHBOROUGH LE11 3TULEICSENGLAND

The paper presents a parallel algorithm design for real-time implementation of arithmetic coding. The implementation comprises a parallelprocessing array arranged in a tree structure. Within each cycle, a group of input symbols can be encoded. This increases the arithmetic coding speed substantially. Details of a fixed-precision algorithm design, its implementation and simulation of its performance are reported.

关键词： ARRAY PROCESSING arithmetic coding

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A VLSI architecture for arithmetic coding of multilevel images

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING 1998年第1期45卷 163-168页

作者： Boo, M Bruguera, JD Lang, T Univ Calif Irvine Dept Elect & Comp Engn Irvine CA 92664 USA

We describe a VLSI architecture of an arithmetic coder for a multilevel alphabet (256 symbols) that includes the storing and updating of probabilities, the updating of the interval, and the correction of the codeword, The architecture is based on the utilization of redundant arithmetic, and the development of new schemes for storing and updating the cumulative probabilities and updating the range and left point of the current interval. The proposed implementation is compared with one that does not include these improvements, and is shown to result in a significantly lower complexity and shorter cycle.

关键词： arithmetic coding redundant representation VLSI architecture

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A modified image selective encryption-compression technique based on 3D chaotic maps and arithmetic coding

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MULTIMEDIA TOOLS AND APPLICATIONS 2019年第14期78卷 19229-19252页

作者： Darwish, Saad Mohamed Alexandria Univ Inst Grad Studies & Res Dept Informat Technol 163 Horreya AvePOB 832 Alexandria 21526 Egypt

The advances in digital image processing and communications have created a great demand for real-time secure image transmission over the networks. However, the development of effective, fast and secure dependent image compression encryption systems are still a research problem as the intrinsic features of images such as bulk data capacity and high correlation among pixels hinds the use of the traditional joint encryption compression methods. A new approach is suggested in this paper for partial image encryption compression that adopts chaotic 3D cat map to de-correlate relations among pixels in conjunction with an adaptive thresholding technique that is utilized as a lossy compression technique instead of using complex quantization techniques and also as a substitution technique to increase the security of the cipher image. The proposed scheme is based on employing both of lossless compression with encryption on the most significant part of the image after contourlet transform. However the least significant parts are lossy compressed by employing a simple thresholding rule and arithmetic coding to render the image totally unrecognizable. Due to the weakness of 3D cat map to chosen plain text attack, the suggested scheme incorporates a mechanism to generate random key depending on the contents of the image (context key). Several experiments were done on benchmark images to insure the validity of the proposed technique. The compression analysis and security outcomes indicate that the suggested technique is an efficacious and safe for real time image's applications.

关键词： Cryptography Joint compression encryption Chaotic maps Contourlet transform Thresholding arithmetic coding

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