In this paper, a dynamic user hierarchy mechanism based on arithmetic coding is proposed. Through careful design of keys, some economic keys are obtained. In our scheme, the relationship between two users can be easil...
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In this paper, a dynamic user hierarchy mechanism based on arithmetic coding is proposed. Through careful design of keys, some economic keys are obtained. In our scheme, the relationship between two users can be easily revealed by evaluating a simple formula to the relative key. In addition, whenever a new user is inserted into the user hierarchy system, the corresponding keys can be determined quickly without changing the existing keys except for the last existing key. Furthermore, the keys proposed by us are drastically reduced from the previous work. (C) 1999 Elsevier Science Ltd. All rights reserved.
In video coding systems using adaptive arithmetic coding to compress texture information, the employed symbol probability models need to be retrained every time the coding process moves into an area with different tex...
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ISBN:
(纸本)9781457705397
In video coding systems using adaptive arithmetic coding to compress texture information, the employed symbol probability models need to be retrained every time the coding process moves into an area with different texture. To avoid this inefficiency, we propose to replace the probability models used in the original coder with multiple switchable sets of probability models. We determine the model set to use in each spatial region in an optimal manner, taking into account the additional signaling overhead. Experimental results show that this approach, when applied to H. 264/AVC's context-based adaptive binary arithmetic coder (CABAC), yields significant bit-rate savings, which are comparable to or higher than those obtained using alternative improvements to CABAC previously proposed in the literature.
In this paper, a field-programmable gate array (FPGA) based enhanced architecture of the arithmetic coder is proposed, which processes two symbols per clock cycle as compared to the conventional architecture that proc...
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ISBN:
(纸本)9781424442966
In this paper, a field-programmable gate array (FPGA) based enhanced architecture of the arithmetic coder is proposed, which processes two symbols per clock cycle as compared to the conventional architecture that processes only one symbol per clock. The input to the arithmetic coder is from the bit-plane coder, which generates more than two context-decision pairs per clock cycle. But due to the slow processing speed of the arithmetic coder, the overall encoding becomes slow. Hence, to overcome this bottleneck and speed up the process, a two-symbol architecture is proposed which not only doubles the throughput, but also can be operated at frequencies greater than 100 MHz. This architecture achieves a throughput of 210 Msymbols/sec and the critical path is at 9.457 ns.
We propose a distributed source coding system for data collected by sensor networks. It uses a feedback channel between the sensors and the gateway node (i.e., the joint decoder) but, unlike previous systems, the enco...
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ISBN:
(纸本)9781424417650
We propose a distributed source coding system for data collected by sensor networks. It uses a feedback channel between the sensors and the gateway node (i.e., the joint decoder) but, unlike previous systems, the encoding process is driven by the decoder. Compression is performed using distributed arithmetic coding, which is extended to adaptively estimate the source probabilities. Specifically, the decoder estimates marginal and conditional probabilities, and sends them back to the sensors to drive the distributed arithmetic coding process. This reduces the decoding delay, and potentially eliminates the need of rate-compatible Slepian-Wolf codes.
The paper proposes a Steganography scheme which focuses on enhancing the embedding efficiency. There are only limited ways on which one can alter the cover image contents. So, for reaching a high embedding capacity, i...
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ISBN:
(纸本)9783319120126;9783319120119
The paper proposes a Steganography scheme which focuses on enhancing the embedding efficiency. There are only limited ways on which one can alter the cover image contents. So, for reaching a high embedding capacity, in the proposed method, the data is compressed using SPIHT algorithm and arithmetic coding. After which the information is embedded into the cover medium. The proposed method suggests an efficient strategy for hiding an image into a cover image of same size without much distortion and could be retrieved back successfully. The advantage of the system is that the cover medium size is reduced to the same size of the input image where in normal cases it is twice or even more. Also the cover image could be recovered from the original stego-image.
The contextual coding of data requires in general a step which reduces the vast variety of possible contexts down to a feasible number. This paper presents a new method for non-uniform quantisation of contexts, which ...
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ISBN:
(纸本)9781479928934
The contextual coding of data requires in general a step which reduces the vast variety of possible contexts down to a feasible number. This paper presents a new method for non-uniform quantisation of contexts, which adaptively merges adjacent intervals as long as the increase of the contextual entropy is negligible. This method is incorporated in a framework for lossless image compression. In combination with an automatic determination of model sizes for histogram-tail truncation, the proposed approach leads to a significant gain in compression performance for a wide range of different natural images.
The Time-Warped Modified Discrete Cosine Transform (TW-MDCT) improves the energy compaction for harmonic signals with varying fundamental frequency compared to the plain MDCT. Adaptive context based entropy coding has...
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ISBN:
(纸本)9781479903566
The Time-Warped Modified Discrete Cosine Transform (TW-MDCT) improves the energy compaction for harmonic signals with varying fundamental frequency compared to the plain MDCT. Adaptive context based entropy coding has the potential to provide higher gain over memoryless entropy coding. But in combination with the TW-MDCT, the context based adaptive coding may lead to suboptimal coding. This paper presents an algorithm for improving the context for the TW-MDCT. This is mainly achieved by exploiting already available information on the frequency variation needed by the TW-MDCT. This results in an improved entropy coding.
This paper investigates the algorithmic complexity of arithmetic coding in the new H264 video coding standard and proposes a coprocessor to reduce it by more than an order of magnitude. The coprocessor is based on an ...
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ISBN:
(纸本)0780388380
This paper investigates the algorithmic complexity of arithmetic coding in the new H264 video coding standard and proposes a coprocessor to reduce it by more than an order of magnitude. The coprocessor is based on an innovative algorithm named as the MZ-coder and maintains the original coding efficiency with a multiplication-free, non-stalling, fully pipelined architecture with modest hardware requirements. The coprocessor delivers a constant throughput for both coding and decoding of 1 bit per cycle and can be attached to a controlling CPU whose ISA has been extended with arithmetic coding instructions.
Distributed arithmetic coding (DAC) is an effective implementation of Slepian-Wolf problem. In this paper, the coding theory of DAC is introduced including two implements for asymmetric Slepian-Wolf problem, Distribut...
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ISBN:
(纸本)9783642352850
Distributed arithmetic coding (DAC) is an effective implementation of Slepian-Wolf problem. In this paper, the coding theory of DAC is introduced including two implements for asymmetric Slepian-Wolf problem, Distributed Overlap arithmetic coding (DOAC) and Distributed Quasi-arithmetic coding (DQAC). Both of the implementation schemes are analyzed. The advantages and disadvantages of them are compared and discussed. Then an improved scheme with easier encoding and decoding is proposed. Simulation results show that the proposed scheme is better than DOAC and DQAC.
The aim of this thesis is to investigate possibilities for creating parallel arithmetic coding implementation and measure performance improvements. In the first part, short overview of arithmetic coding with its seria...
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The aim of this thesis is to investigate possibilities for creating parallel arithmetic coding implementation and measure performance improvements. In the first part, short overview of arithmetic coding with its serial implementation (FastAC by Amir Said) is presented. The thesis then describes principles of work with GPUs and identifies possibilities of algorithm improvement and parallelization. Several parallel implementations are given, with varying performance improvements and occasional drawbacks. In conclusion, thesis provides results of performance tests of our implementation, as well as discussion about feasibility of applying GPU-oriented version of algorithm instead of serial one in real-world applications. Powered by TCPDF (***)
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