This study introduces an architecture for motion estimation block of the video encoder using adaptive rood pattern search (arps) algorithm. The architecture has been designed for field programmable gate array (FPGA) a...
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This study introduces an architecture for motion estimation block of the video encoder using adaptive rood pattern search (arps) algorithm. The architecture has been designed for field programmable gate array (FPGA) as well as application specific integrated circuit (ASIC) implementations. Experimental results show that the speed of arps algorithm is ahead of several existing fast motion estimation algorithms without compromising the peak signal-to-noise ratio values. The Virtex-4 FPGA implementation of the proposed architecture using Xilinx 14.2 attains a maximum frequency of 103 MHz with <3% usage of slices. ASIC implementation of the proposed architecture with Synopsys design vision tool (0.18 mu m) using 100 MHz frequency involves power consumption of 4.54 mW and occupies 0.073 mm(2). A maximum frequency of 333 MHz has been achieved for the ASIC implementation with 16 x 16 blocks and it can process 651 frames of slow motion video such as Akiyo and 280 frames of fast motion video such as Football of CIF format (352 x 288 resolution) per second. Moreover, the ASIC implementation can process up to 31 frames of HD (1920 x 1080 resolution) video per second. Hence, the proposed architecture fits well in applications such as video conferencing and video phones.
Block-based motion estimation plays a significant role in video codecs by exploiting and reducing the temporal redundancies that exist between consecutive frames in a video sequence. Adaptive Rood Pattern Search (arps...
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Block-based motion estimation plays a significant role in video codecs by exploiting and reducing the temporal redundancies that exist between consecutive frames in a video sequence. Adaptive Rood Pattern Search (arps) is one of the most popular fast motion estimation algorithms. In this paper, VLSI design for the arps algorithm is proposed that involves reasonably limited hardware resource without compromising the real-time speed for transmitting HD videos. To tackle the adaptive nature of the algorithm, the proposed design avoids systolic arrays and introduces novel pattern generation methodology that can tackle the adaptive nature of the algorithm. Further, the design incorporates interleaved memory organization with a well-defined sharing strategy to re-use data and ensures high throughput. Working at a frequency of 112 MHz, the present design can process 30 Full HD 1080p (1920x1080) frames using only 47.15 K gates. Hence, the proposed VLSI architecture can be incorporated in video codecs that can be suitably used in devices like camcorders, tablets and smart phones. (C) 2016 Elsevier B.V. All rights reserved.
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