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A high-throughput asic processor for 8 x 8 transform coding in H.264/AVC

SIGNAL PROCESSING-IMAGE COMMUNICATION 2011年第2期26卷 93-104页

作者： Michell, Juan A. Solana, Jose M. Ruiz, Gustavo A. Univ Cantabria Fac Ciencias Dept Elect & Computadores E-39005 Santander Spain

In July 2004, a new amendment called Fidelity Range Extensions (FRExt) was added to the H.264/AVC as a standardization initiative motivated by the rapidly growing demands when coding higher-fidelity video material. One improvement present in the FRExt is the inclusion of a new 8 x 8 integer transform that only makes use of additions and shifters to avoid mismatches between encoders and decoders. This paper presents a processor with pipeline architecture for real-time implementation of the complete process for the 8 x 8 Transform Coding in H.264: forward 8 x 8 integer transform, quantization and scaling, re-scaling, inverse 8 x 8 integer transform and reconstruction of the image block. This architecture has been conceived with the aim of achieving a high operation frequency and high throughput without increasing the hardware complexity. In order to achieve an efficient implementation, hardware solutions have been developed for the different circuit modules. 8 x 8 forward and inverse transforms are calculated using the separability property with architecture more suitable for pipeline schemes made up of two 1D processors and a transpose register array. New expressions for forward quantization and scaling are presented allowing efficient hardware implementation by avoiding the sign conversion. The inverse quantization has also been optimized in terms of hardware complexity by minimizing the involved arithmetic operations. Furthermore, an exhaustive analysis in the dynamic range of the datapath is made to fix the optimum bus widths with the aim of reducing the size of the circuit while avoiding overflow. Finally, the critical paths of the various computing units have been carefully analyzed and balanced using a pipeline scheme in order to maximize the operation frequency without introducing an excessive latency. A prototype with the proposed architecture has been synthesized in a 130 nm HCMOS technology process, which achieves a maximum speed of 330 MHz with a throughpu

关键词： H.264/AVC 8 x 8 integer cosine transform Quantization Transform coding asic processor

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A High Throughput processor Chip for Transform and Quantization Coding in H.264/AVC

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2013年第1期70卷 59-73页

作者： Manzano, Miguel A. Michell, Juan A. Ruiz, Gustavo A. Univ Cantabria Fac Ciencias Dpto Elect & Comp E-39005 Santander Spain

This paper presents an asic processor chip for real-time implementation of the computing of the complete process of forward transform, quantization, inverse transform, dequantization, and reconstruction of a 16 x 16 macroblock in full compliance with the H.264/AVC video coding standard. This processor is capable of processing 4 x 4 blocks without interruption, with a parallelism in the data-path of 16 data/cycle, in a pipeline architecture with the twofold aim of achieving high operation frequency and high throughput. To implement the four 4 x 4 transforms and two 2 x 2 transforms required in the H.264/AVC coding system, two configurable multitransform direct 2-D architectures are used, one for forward and another for inverse. Moreover, a reduction in hardware is achieved by reformulating of quantization and dequantization equations and appropriately adjusting the datapath bus widths. A prototype of this processor chip was fabricated in the HCMOS9 STMicroelectronics 130 nm standard cell technology. The latency for 16 x 16 macroblocks is 26 clock cycles in normal mode and 42 in Intra 16 x 16 mode with a maximum operating frequency of 280 MHz and a throughput of 4,480 Mpixels/s. As a result, our processor chip is able to support the UHDTV 7680 x 4320@60 Hz (3 G sample/s) format requirement.

关键词： H.264 Integer transform Quantization Transform coding asic processor

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