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8th International Workshop on Accelerator Programming using Directives (WACCPD)

作者： Stulajter, Miko M. Caplan, Ronald M. Linker, Jon A. Predict Sci Inc 9990 Mesa Rim RdSuite 170 San Diego CA 92121 USA

ISBN: (纸本)9783030977597;9783030977580

Recently, there has been growing interest in using standard language constructs (e.g. C++'s Parallel Algorithms and Fortran's do concurrent) for accelerated computing as an alternative to directive-based APIs (e.g. OpenMP and OpenACC). These constructs have the potential to be more portable, and some compilers already (or have plans to) support such standards. Here, we look at the current capabilities, portability, and performance of replacing directives with Fortran's do concurrent using a mini-app that currently implements OpenACC for GPU-acceleration and OpenMP for multi-core CPU parallelism. We replace as many directives as possible with do concurrent, testing various configurations and compiler options within three major compilers: GNU's gfortran, NVIDIA's nvfortran, and Intel's ifort. We find that with the right compiler versions and flags, many directives can be replaced without loss of performance or portability, and, in the case of nvfortran, they can all be replaced. We discuss limitations that may apply to more complicated codes and future language additions that may mitigate them. The software and Singularity/Apptainer containers are publicly provided to allow the results to be reproduced.

关键词： accelerated computing OpenMP OpenACC do concurrent standard language parallelism

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An FPGA-based binary neural network accelerator with enhanced hardware efficiency and data reuse

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MICROELECTRONICS JOURNAL 2025年 156卷

作者： Zhang, Dezheng Cen, Rui Pu, Han Wan, Rui Wang, Dong Beijing Jiaotong Univ Inst Informat Sci Beijing 100044 Peoples R China Network Technol Beijing Key Lab Adv Informat Sci Beijing 100044 Peoples R China Tiangong Univ Sch Comp Sci & Technol Tianjin 300387 Peoples R China

Binary neural network (BNN) algorithms have gained significant attention due to their low computational complexity and improved accuracy. Field-programmable gate array (FPGA)-based accelerators for BNNs typically transform binary operations into XNOR and popcount operations, efficiently utilizing logic resources. However, fixed-point operations in the first and final layers result in high hardware costs. Moreover, frequent off-chip memory access, particularly for shortcut operations, can severely limit throughput. This paper introduces a hardware-efficient FPGA-based BNN accelerator with minimized off-chip memory access. The first layer's inputs are binarized using an enhanced thermometer encoding scheme, enabling all convolution layers to be executed on a unified binary computing unit. A multi-mode computing unit is designed to perform both ReAct parametric rectified linear unit (RPReLU) and linear operations using shared hardware multipliers, which maximizes hardware reuse. To address bandwidth limitations, we implement a dynamic data buffering architecture, featuring high-bandwidth and high-volume buffers for caching intra-layer and cross-layer data, respectively. The accelerator supports two data buffering schemes, and the one minimizing the off-chip memory access is selected for each convolution layer. The accelerator is evaluated on an Alinx AXU3EGB development board and a custom development board with a Xilinx XC7V690T device, respectively. Experiments on ImageNet demonstrate 69.34% accuracy, with frames per second (FPS) of 129.1 and 405.6 on the ZU3EG and XC7V690T devices, respectively. Compared to the state-of-the-art design, our accelerator achieves 2.7x FPS on the same FPGA device.

关键词： Binary neural network FPGA circuit design accelerated computing High-level synthesis (HLS)

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On the impact of quantum computing technology on future developments in high-performance scientific computing

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ETHICS AND INFORMATION TECHNOLOGY 2017年第4期19卷 253-269页

作者： Moller, Matthias Vuik, Cornelis Delft Univ Technol Delft Inst Appl Math Mekelweg 4 NL-2628 CD Delft Netherlands

Quantum computing technologies have become a hot topic in academia and industry receiving much attention and financial support from all sides. Building a quantum computer that can be used practically is in itself an outstanding challenge that has become the 'new race to the moon'. Next to researchers and vendors of future computing technologies, national authorities are showing strong interest in maturing this technology due to its known potential to break many of today's encryption techniques, which would have significant and potentially disruptive impact on our society. It is, however, quite likely that quantum computing has beneficial impact on many computational disciplines. In this article we describe our vision of future developments in scientific computing that would be enabled by the advent of software-programmable quantum computers. We thereby assume that quantum computers will form part of a hybrid accelerated computing platform like GPUs and co-processor cards do today. In particular, we address the potential of quantum algorithms to bring major breakthroughs in applied mathematics and its applications. Finally, we give several examples that demonstrate the possible impact of quantum-accelerated scientific computing on society.

关键词： Quantum computing Quantum algorithms Scientific computing High-performance computing accelerated computing Applied mathematics

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Design Considerations for GPU-based Mixed Integer Programming on Parallel computing Platforms 21

Design Considerations for GPU-based Mixed Integer Programmin...

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50th International Conference on Parallel Processing (ICPP)

作者： Perumalla, Kalyan Alam, Maksudul Oak Ridge Natl Lab Oak Ridge TN 37830 USA

ISBN: (纸本)9781450384414

Mixed Integer Programming (MIP) is a powerful abstraction in combinatorial optimization that finds real-life application across many significant sectors. The recent proliferation of graphical processing unit (GPU)-based accelerated computing architectures in large-scale parallel computing or supercomputing presents new opportunities as well as challenges in the advancement of MIP solver technology to effectively use the new accelerated computing platforms and scale to large parallel systems. Here, we recount the conventional processor-based strategies and focus on configurations where the most promising intersection lies between parallel MIP solver approaches and the specific strengths of accelerated parallel platforms. We note that the best potential lies in solving problems whose individual matrix sizes (of the linear program relaxation) fit entirely within one accelerator's memory and whose branch-and-bound (or branch-and-cut) trees cannot be fully contained within a small number of computational nodes. Additionally, we identify ideal features of computational linear algebra support on GPU accelerators that would help advance this direction of scalable parallel solution of MIP problems on GPU-based accelerated computing architectures.

关键词： accelerated computing Parallel computing Mixed Integer Programming Branch-and-Bound Graphical Processing Units

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accelerated application development: The ORNL Titan experience

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COMPUTERS & ELECTRICAL ENGINEERING 2015年 46卷 123-138页

作者： Joubert, Wayne Archibald, Rick Berrill, Mark Brown, W. Michael Eisenbach, Markus Grout, Ray Larkin, Jeff Levesque, John Messer, Bronson Norman, Matt Philip, Bobby Sankaran, Ramanan Tharrington, Arnold Turner, John Oak Ridge Natl Lab Oak Ridge TN 37831 USA Cray Inc Knoxville TN USA Natl Renewable Energy Lab Golden CO 80401 USA NVIDIA Corp Oak Ridge TN 37831 USA

The use of computational accelerators such as NVIDIA GPUs and Intel Xeon Phi processors is now widespread in the high performance computing community, with many applications delivering impressive performance gains. However, programming these systems for high performance, performance portability and software maintainability has been a challenge. In this paper we discuss experiences porting applications to the Titan system. Titan, which began planning in 2009 and was deployed for general use in 2013, was the first multi-petaflop system based on accelerator hardware. To ready applications for accelerated computing, a preparedness effort was undertaken prior to delivery of Titan. In this paper we report experiences and lessons learned from this process and describe how users are currently making use of computational accelerators on Titan. (C) 2015 Elsevier Ltd. All rights reserved.

关键词： High performance computing accelerated computing GPU graphics processing units Science applications Code refactoring Software optimization

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Flynn's Reconciliation: Automating the Register Cache Idiom for Cross-accelerator Programming

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2021年第3期18卷 1–26页

作者： Thuerck, Daniel Weber, Nicolas Bifulco, Roberto NEC Labs Europe Kurftirsten Anlage 36 Heidelberg Germany Tech Univ Darmstadt Darmstadt Germany

A large portion of the recent performance increase in the High Performance computing (HPC) and Machine Learning (ML) domains is fueled by accelerator cards. Many popular ML frameworks support accelerators by organizing computations as a computational graph over a set of highly optimized, batched general-purpose kernels. While this approach simplifies the kernels' implementation for each individual accelerator, the increasing heterogeneity among accelerator architectures for HPC complicates the creation of portable and extensible libraries of such kernels. Therefore, using a generalization of the CUDA community's warp register cache programming idiom, we propose a new programming idiom (CoRe) and a virtual architecture model (PIRCH), abstracting over SIMD and SIMT paradigms. We define and automate the mapping process from a single source to PIRCH's intermediate representation and develop backends that issue code for three different architectures: Intel AVX512, NVIDIA GPUs, and NEC SX-Aurora. Code generated by our source-to-source compiler for batched kernels, borG, competes favorably with vendor-tuned libraries and is up to 2x faster than hand-tuned kernels across architectures.

关键词： accelerated computing GPGPU warp-register cache batched kernels SIMT SIMD cross-architecture compilation source-to-source compiler

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Fine-grain Quantitative Analysis of Demand Paging in Unified Virtual Memory

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2024年第1期21卷 1-24页

作者： Allen, Tyler Cooper, Bennett Ge, Rong Univ N Carolina Charlotte NC USA Clemson Univ Clemson SC USA Univ N Carolina 210E Woodward Hall Charlotte NC 28223 USA Clemson Univ 100 McAdams Hall Clemson SC 29634 USA

The abstraction of a shared memory space over separate CPU and GPU memory domains has eased the burden of portability for many HPC codebases. However, users pay for ease of use provided by system-managed memory with a moderate-to-high performance overhead. NVIDIA Unified Virtual Memory ( UVM) is currently the primary real-world implementation of such abstraction and offers a functionally equivalent testbed for in-depth performance study for both UVMand future Linux HeterogeneousMemoryManagement (HMM) compatible systems. The continued advocacy for UVM and HMM motivates improvement of the underlying system. We focus on UVM-based systems and investigate the root causes of UVM overhead, a non-trivial task due to complex interactions of multiple hardware and software constituents and the desired cost granularity. In our prior work, we delved deeply into UVM system architecture and showed internal behaviors of page fault servicing in batches. We provided quantitative evaluation of batch handling for various applications under different scenarios, including prefetching and oversubscription. We revealed that the driver workload depends on the interactions among application access patterns, GPU hardware constraints, and host OS components. Host OS components have significant overhead present across implementations, warranting close attention. This extension furthers our prior study in three aspects: fine-grain cost analysis and breakdown, extension to multiple GPUs, and investigation of platforms with different GPU-GPU interconnects. We take a top-down approach to quantitative batch analysis and uncover how constituent component costs accumulate and overlap, governed by synchronous and asynchronous operations. Our multi-GPU analysis shows reduced cost of GPU-GPU batch workloads compared to CPU-GPU workloads. We further demonstrate that while specialized interconnects, NVLink, can improve batch cost, their benefits are limited by host OS software overhead and GPU oversubscrip

关键词： Unified Virtual Memory Heterogeneous Memory Management Virtual Memory GPGPU accelerated computing

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Parallel Genetic Algorithm Interface II: A novel computational tool for accelerated simulation-based optimization

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CHEMICAL ENGINEERING RESEARCH & DESIGN 2024年 207卷 29-48页

作者： Furda, Patrik Variny, Miroslav Mysiak, Juraj Slovak Univ Technol Bratislava Fac Chem & Food Technol Dept Chem & Biochem Engn Radlinskeho 9 Bratislava 81237 Slovakia

The ever increasing power of computational tools encouraged by the general need for development of more sustainable technologies fuels the interest in modern optimization approaches. While simulation-based optimization has been receiving considerable attention in the past decades, it still struggles to overcome some challenges, namely excessive computation time. This study proposes a novel optimization interface, the Parallel Genetic Algorithm Interface II (PAGAN-II), which utilizes parallelization of flowsheet simulations to drastically reduce the optimization time without the need to use clustered CPUs and/or modified optimization algorithms. Results of a detailed performance study showed up to 2100% increase in computation rate when optimizing demanding process flowsheets;and approximately 300% increase when optimizing simple ones. Capabilities of the proposed interface were demonstrated by optimization of a 5 MTPA C3MR LNG technology processing 12 different feedstocks, where a 15-30% decrease in the specific energy consumption was achieved. At the same time, the algorithm increased the optimization speed 13-fold compared to the traditional approach. This translates into a reduction of optimization time from 69 days of non-stop computation to approximately 7 days.

关键词： accelerated computing Aspen Plus Genetic algorithm Simulation -based optimization Software linking

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Model Predictive Decision-Making Considering Lane-Changing Time Under Emergency Collision Avoidance for Intelligent Vehicles

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2024年第9期71卷 11250-11261页

作者： Dai, Qikun Liu, Jun Guo, Hongyan Chen, Hong Cao, Dongpu Jilin Univ Coll Commun Engn Natl Key Lab Automot Chassis Integrat & Bion Campus NanLing Changchun 130025 Peoples R China Jilin Univ Coll Automot Engn Campus NanLing Changchun 130025 Peoples R China Jilin Univ Coll Commun Engn Campus NanLing Changchun 130025 Peoples R China Tongji Univ Coll Elect & Informat Engn Shanghai 201804 Peoples R China Univ Waterloo Dept Mech & Mechatron Engn Waterloo ON N2L 3G1 Canada

When a vehicle faces an imminent collision, it becomes imperative for intelligent vehicles to make emergency collision avoidance decisions in order to mitigate traffic accidents and reduce injuries. To address collision avoidance in emergency scenarios, this study proposes a model predictive decision-making (MPDM) approach that incorporates the consideration of lane-changing time. First, a simplified integrated longitudinal and lateral decision-making model is established, and its accuracy is validated through comparison with real vehicle data. Second, a mixed integer nonlinear MPDM is designed to optimize emergency collision avoidance decisions. Within this framework, the minimum lane-changing time for intelligent vehicles is analytically derived based on vehicle dynamics, taking into account varying speeds and adhesion coefficients. Third, by reducing the dimensionality of the lane-changing time optimization variables, an equivalent suboptimization problem is introduced, which consequently diminishes the computational complexity of solving the optimization problem. Finally, a comparative analysis was performed between the MPDM method and several alternative approaches, employing Simulink-SCANeR cosimulation. Furthermore, the MPDM method was validated on a real vehicle. The results obtained highlight a significant enhancement in the safety and stability of collision avoidance due to the MPDM.

关键词： Decision making Collision avoidance Intelligent vehicles Vehicle dynamics Roads Predictive models Radar tracking accelerated computing collision avoidance decision-making intelligent vehicle mixed integer nonlinear programming model predictive control (MPC)

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The zero-tax data center: a use case through quantum resilient communications 24

The zero-tax data center: a use case through quantum resilie...

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24th International Conference on Transparent Optical Networks (ICTON)

作者： Lawo, Daniel Podles, Michal Frantz, Raphael Aguilera, Abraham Cano Iliadis-Apostolidis, Dismothenis Sanchez, Jeronimo Kosta, Sokol Monroy, Idelfonso Tafur Luis Imana, Jose Olmos, J. J. Vegas Eindhoven Univ Technol Dept Elect Engn Eindhoven Netherlands Aalborg Univ Dept Elect Syst Copenhagen Denmark Univ Complutense Madrid Dept Comp Architecture & Automat Madrid Spain NVIDIA Corp Software Architecture Ofer Ind Pk Yokneam Israel

ISBN: (纸本)9798350377330;9798350377323

Data centers, cloud and edge computing platforms are absorbing heavy AI-based workloads. This raises two concerns: how to reduce the networking overhead by host processors in order to focus only on AI-processing, and how to provide quantum resilient level protection for any connection running such workloads. In this paper, we will show case the concept of zero-tax data center, which is achieved through offloading of networking functions from the host to the network. In particular, the implementation of postquantum cryptography algorithms providing quantum resilient links and how the processing its complex processing is moved from host to network through the utilization of data-processing units.

关键词： data center networking accelerated computing high performance computing postquantum cryptography

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