A low-power (similar to 600nW), fully analog integrated architecture for a voting classification algorithm is introduced. It can effectively handle multiple-input features, maintaining exceptional levels of accuracy a...
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A low-power (similar to 600nW), fully analog integrated architecture for a voting classification algorithm is introduced. It can effectively handle multiple-input features, maintaining exceptional levels of accuracy and with very low power consumption. The proposed architecture is based on a versatile Voting algorithm that selectively incorporates one of three key classification models: Bayes or Centroid, or, the Learning Vector Quantization model;all of which are implemented using Gaussian-likelihood and Euclidean distance functioncircuits, as well as a current comparison circuit. To evaluate the proposed architecture, a comprehensive comparison with popular analog classifiers is performed, using real-life diabetes dataset. All model architectures were trained using Python and compared with the software-based classifiers. The circuit implementations were performed using the TSMC 90 nm CMOS process technology and the Cadence IC Suite was utilized for the design, schematic and post-layout simulations. The proposed classifiers achieved sensitivity of >= and specificity of >= 89.7%.
In this article (based on transconductance adjustment) novel low power, programmable circuits such as switched transconductance and neuron structures that set foundations for low power VLSI sampled data filtering circ...
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In this article (based on transconductance adjustment) novel low power, programmable circuits such as switched transconductance and neuron structures that set foundations for low power VLSI sampled data filtering circuits and neural networks are proposed. The switched transconductance integrator structures are presented and their performances are compared to switched current counterparts. Also the analog circuits for activationfunction and programmable weight synaptic connections are presented and discussed. A qualitative comparison is made between standard and proposed circuits.
With several advancements in medical science being carried out over the past few decades, there has been a constant need to process information artificially, the way it is processed inside the human body. This inheren...
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With several advancements in medical science being carried out over the past few decades, there has been a constant need to process information artificially, the way it is processed inside the human body. This inherent attribute of Artificial Intelligence (AI) is achieved in practice using Artificial Neural Networks (ANNs). ANNs have been around since 1943 and used since then for artificial information processing and neural *** thesis focuses on the hardware implementation of an artificial neural network using CMOS technology. The design is carried out in the analog domain to exploit certain advantages of analog integrated circuit design, such as, high efficiency, in terms of area and power, and ease of computation. The neural architecture designed is a multilayer feedforward neural network to solve the XOR classification problem, which serves as a benchmark for several complex classification problems that are not linearly separable. Each component circuit of the network, such as the synapse circuit that performs the multiplication operation and the non-linear activation function circuit that acts as squashing function, is designed using MOSFETs operating in the sub-threshold (weak inversion) *** schematic designs are carried out using Cadence OrCAD Capture version 16.6 EDA software and simulated using PSPICE version 16.6, an in-built simulation tool within OrCAD capture. The layout of the individual components and the overall schematic is also done using Electric VLSI Design software version 9.06 on a 200 nm design scale. A consistency check is carried out to ensure equivalency of layout with the schematic, for a potential scope towards chip fabrication using Metal Oxide Semiconductor Implementation Service (MOSIS) foundry. The layout of the proposed neural architecture is found to occupy an area of 0.065 〖mm〗^2, indicating design compactness to a moderate level.
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