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TTQR: A Traffic- and Thermal-Aware Q-routing for 3D Network-on-Chip

SENSORS 2022年第22期22卷 8721页

作者： Liu, Hanyan Chen, Xiaowen Zhao, Yunping Li, Chen Lu, Jianzhuang Natl Univ Def Technol Coll Comp Sci Changsha 410073 Peoples R China

The die-stacking structure of 3D network-on-chips (3D NoC) leads to high power density and unequal thermal conductance between different layers, which results in low reliability and performance degradation of 3D NoCs. Congestion-aware adaptive routing, which is capable of balancing the network's traffic load, can alleviate congestion and thermal problems so as to improve the performance of the network. In this study, we propose a traffic- and thermal-aware Q-routing algorithm (TTQR) based on Q-learning, a reinforcement learning method. The proposed algorithm saves the local traffic status and the global temperature information to the Q1-table and Q2-table, respectively. The values of two tables are updated by the packet header and saved in a small size, which saves the hardware overhead. Based on the ratio of the Q1-value to the Q2-value corresponding to each direction, the packet's output port is selected. As a result, packets are transferred to the chosen path to alleviate thermal problems and achieve more balanced inter-layer traffic. Through the Access Noxim simulation platform, we compare the proposed routing algorithm with the TAAR routing algorithm. According to experimental results using synthetic traffic patterns, our proposed methods outperform the TAAR routing algorithm by an average of 63.6% and 41.4% in average latency and throughput, respectively.

关键词： 3D network-on-chip adaptive routing algorithm Q-learning Q-routing

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Data and Fault Aware routing algorithm for NoC Based Approximate Computing 22

Data and Fault Aware Routing Algorithm for NoC Based Approxi...

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Proceedings of the 17th ACM International Symposium on Nanoscale Architectures

作者： Ibrahim Krayem Romain Mercier Cédric Killian Angeliki Kritikakou Daniel Chillet Inria IRISA Univ Rennes Lannion France

ISBN: (纸本)9781450399388

Due to transistor shrinking and core number increasing in System-on-Chip (SoC), fault tolerance has become a critical concern. Given the amount of data communications on such architectures, Network-on-Chips (NoCs) lead a crucial role in terms of performance. Even if fault correction approaches have been developed, they cannot efficiently address several permanent faults on NoC, due to their high hardware costs and correction limitations. In parallel, Approximate Computing domain considers applications that can tolerate errors, hence allowing fault mitigation instead of correction. This latter brings the opportunity of low implementation cost techniques to improve the reliability of *** this work, we propose a routing technique which selects a path between cores according to data type and permanent fault positions. Error tolerant data are able to cross faulty paths by using a bit-shuffling error mitigation technique. Critical data circumvent faulty paths or are duplicated and shuffled in case there is no other correct path available. Results show that our routing technique allows to maintain all the communication paths within the NoC for a large amount of permanent errors. To further evaluate the behavior of the proposed technique, we performed a comprehensive analysis of the technique on the packet latency and saturation injection rate with respect to the number of faults and traffic type.

关键词： fault mitigation approximate computing adaptive routing algorithm bit-shuffling network-on-chip

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An adaptive congestion-aware routing algorithm based on network load for wireless routers in wireless network-on-chip

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2018年 97卷 25-37页

作者： Mamaghani, Shokoofeh Mikaeeli Jamali, Mohammad Ali Jabraeil Islamic Azad Univ Tabriz Branch Dept Comp Engn Tabriz Iran Islamic Azad Univ Shabestar Branch Dept Comp Engn Shabestar Iran

Wireless Network-on-Chip (WiNoC) is regarded as one of the promising alternative approaches for sorting out the issues of latency and power consumption in the conventional Network-on-Chip (NoC). Despite the additional bandwidth of wireless channels on a chip, wireless routers (WRs) are prone to congestion in WiNoC due to the limited number of wireless channels on a chip and the shared use of these channels among all the cores. In this paper, an adaptive congestion-aware routing algorithm consistent with traffic load is proposed for solving the congestion problem of WRs. The proposed algorithm selects source-destination pairs with the longest wired hop distance for using wireless channels. The number of selected packets is determined based on the wireless channel bandwidth and the network traffic load. Simulation results show up to 65% latency improvement, 16% wired/wireless link utilization improvement and a saturation throughput increase of approximately 11%. (C) 2018 Elsevier GmbH. All rights reserved.

关键词： Wireless network-on-chip adaptive routing algorithm Congestion control On-chip interconnection network Hybrid NoC

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A Novel Ring-based Small-World NoC for Neuromorphic Processor 32

A Novel Ring-based Small-World NoC for Neuromorphic Processo...

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32nd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)

作者： Qiu, Yuchen Xiao, Chao Peng, LingHui Wang, Junhui Kang, Ziyang Li, Shiming Wang, Lei Natl Univ Def Technol Coll Comp Sci & Technol Changsha Peoples R China

ISBN: (纸本)9781665427012

Neuromorphic computing has shown promise in metrics such as power consumption and parallelism over existing computer systems, which essentially promote the development of neuromorphic processors in recent years. In order to properly place the increasing number of neuron cores and support the inter-core communication, Network-on-Chip (NoC) is widely used in the design of neuromorphic processors. Mesh has historically been used for multi-core NoCs, however, in neuromorphic chips, computation cores are relatively small, mesh-based SNN with high resource occupation limited the peak performance and energy efficiency. Moreover, one of the most significant findings in the neuroscience is that human brain exhibits small-world effect which is originated from the social network, inspired by that, we proposed a composite architecture for neuromorphic processor called the ring-based small-world NoC. Correspondingly, we proposed a routing algorithm to by generating a specific-application routing table in the pre-processing stage. We evaluated the performance such as delay, energy and resource utilization comprehensively based on three spike-based datasets (FSDD, NMNIST and N-TIDIGITS). The experimental results show that the average packet latency and the resource utilization of the proposed network is reduced by up to 18% and 35%, compared to a regular mesh network.

关键词： Neuromorphic computing network-on-chip small-world network ring topology adaptive routing algorithm

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An adaptive Capsule Network for Hyperspectral Remote Sensing Classification

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REMOTE SENSING 2021年第13期13卷

作者： Ding, Xiaohui Li, Yong Yang, Ji Li, Huapeng Liu, Lingjia Liu, Yangxiaoyue Zhang, Ce Guangdong Acad Sci Guangzhou Inst Geog Guangzhou 510070 Peoples R China Southern Marine Sci & Engn Guangdong Lab Guangzho Guangzhou 511458 Peoples R China Guangdong Open Lab Geospatial Informat Technol & Guangzhou 510070 Peoples R China Key Lab Guangdong Utilizat Remote Sensing & Geog Guangzhou 510070 Peoples R China Chinese Acad Sci Northeast Inst Geog & Agroecol Changchun 130102 Peoples R China Jiangxi Normal Univ Sch Geog & Environm Nanchang 330027 Jiangxi Peoples R China Univ Lancaster Lancaster Environm Ctr Lancaster LA1 4YQ England UK Ctr Ecol & Hydrol Lib Ave Lancaster LA1 4AP England

The capsule network (Caps) is a novel type of neural network that has great potential for the classification of hyperspectral remote sensing. However, the Caps suffers from the issue of gradient vanishing. To solve this problem, a powered activation regularization based adaptive capsule network (PAR-ACaps) was proposed for hyperspectral remote sensing classification, in which an adaptive routing algorithm without iteration was applied to amplify the gradient, and the powered activation regularization method was used to learn the sparser and more discriminative representation. The classification performance of PAR-ACaps was evaluated using two public hyperspectral remote sensing datasets, i.e., the Pavia University (PU) and Salinas (SA) datasets. The average overall classification accuracy (OA) of PAR-ACaps with shallower architecture was measured and compared with those of the benchmarks, including random forest (RF), support vector machine (SVM), 1-dimensional convolutional neural network (1DCNN), two-dimensional convolutional neural network (CNN), three-dimensional convolutional neural network (3DCNN), Caps, and the original adaptive capsule network (ACaps) with comparable network architectures. The OA of PAR-ACaps for PU and SA datasets was 99.51% and 94.52%, respectively, which was higher than those of benchmarks. Moreover, the classification performance of PAR-ACaps with relatively deeper neural architecture (four and six convolutional layers in the feature extraction stage) was also evaluated to demonstrate the effectiveness of gradient amplification. As shown in the experimental results, the classification performance of PAR-ACaps with relatively deeper neural architecture for PU and SA datasets was also superior to 1DCNN, CNN, 3DCNN, Caps, and ACaps with comparable neural architectures. Additionally, the training time consumed by PAR-ACaps was significantly lower than that of Caps. The proposed PAR-ACaps is, therefore, recommended as an effective alternative

关键词： capsule network hyperspectral remote sensing adaptive routing algorithm deep learning

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Efficient Design-for-Test Approach for Networks-on-Chip

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IEEE TRANSACTIONS ON COMPUTERS 2019年第2期68卷 198-213页

作者： Wang, Junshi Ebrahimi, Masoumeh Huang, Letian Xie, Xuan Li, Qiang Li, Guangjun Jantsch, Axel Univ Elect Sci & Technol China Chengdu 610054 Sichuan Peoples R China Beijing Zhaoxin Elect Technol Co Ltd Beijing 100084 Peoples R China KTH Royal Inst Technol S-11428 Stockholm Sweden Tech Univ Wien A-1040 Vienna Austria

To achieve high reliability in on-chip networks, it is necessary to test the network continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the number of affected packets can be minimized. However, BISTcauses significant performance loss due to data dependencies. We propose EsyTest, a comprehensive test strategy with minimized influence on system performance. EsyTest tests the data path and the control path separately. The data path test starts periodically, but the actual test performs in the free time slots to avoid deactivating the router for testing. A reconfigurable router architecture and an adaptive fault-tolerant routing algorithm are proposed to guarantee the access to the processing core when the associated router is under test. During the whole test procedure of the network, all processing cores are accessible, and thus the system performance is maintained during the test. At the same time, EsyTest provides a full test coverage for the NoC and a better hardware compatibility comparing with the existing test strategies. Under the PARSEC benchmark and different test frequencies, the execution time increases less than 5 percent at the cost of 9.9 percent more area and 4.6 percent more power in comparison with the execution where no test procedure is applied.

关键词： Network-on-chip non-blocking testing reliability monitoring reconfigurable router architecture adaptive routing algorithm built-in self-test

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DICA: destination intensity and congestion-aware output selection strategy for network-on-chip systems

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IET COMPUTERS AND DIGITAL TECHNIQUES 2019年第4期13卷 335-347页

作者： Mehranzadeh, Amin Khademzadeh, Ahmad Bagherzadeh, Nader Reshadi, Midia Islamic Azad Univ Sci & Res Branch Dept Comp Engn Tehran Iran Iran Telecommun Res Ctr Tehran Iran Univ Calif Irvine Dept Elect Engn & Comp Sci Irvine CA USA

Selection strategy is an essential part of an adaptive routing algorithm that influences the performance of the networks-on-chip (NoC). A selection strategy is used for selecting the best output channel from the available channels according to the network status. This study presents a new output selection strategy called destination intensity and congestion aware (DICA) that uses both local and regional congestion information from adjacent and two hops away neighbours on the path to destination based on the channel and switch information. Also, the proposed output selection strategy uses a new global congestion-aware scheme based on destination node called destination congestion awareness method to distribute traffic more equally over the network. The simulation results show that DICA strategy consistently improves the performance in both throughput and average latency with minimal overhead in terms of area consumption for various synthetic and real application traffic patterns. In addition, the microarchitecture of NoC routers is also presented in this study and it shows that the proposed output selection strategy can be combined with any adaptive routing algorithms. The experimental results show the average delay improvements of DICA to the Bufferlevel, neighbours-on-path, and regional congestion awareness are 87, 57, and 24%, respectively.

关键词： network-on-chip telecommunication congestion control telecommunication network routing telecommunication traffic congestion-aware output selection strategy network-on-chip systems adaptive routing algorithm networks-on-chip output channel network status local congestion information regional congestion information switch information global congestion-aware scheme destination node destination congestion awareness method DICA strategy regional congestion awareness channel information Bufferlevel NoC router microarchitecture output selection strategy destination intensity and congestion aware

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Retunes: Reliable And Energy-Ecient Network-On-Chip Architecture Using adaptive routing And Approximate Communication

Retunes: Reliable And Energy-Ecient Network-On-Chip Architec...

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作者： Padmaja Bhamidipati Ohio University

学位级别：硕士

As the number of processing cores are increasing in a chip multiprocessor (CMP), demand for an energy-efficient and reliable Network-on-Chip (NoC) architecture is increasing. However, the energy consumption of NoC continues to increase with the exponential growth in CMPs. Voltage scaling techniques such as Dynamic Voltage and Frequency Scaling (DVFS) and Near Threshold Voltage (NTV) scaling have been proposed to reduce the energy consumption of NoC by scaling the operating voltage and frequency in proportion to the application demand. Apart from DVFS and NTV scaling, recently, approximate communication has been proposed to boost the power savings and reduce latency in NoC for the applications that are not sensitive to imprecise results within an acceptable variance. As transistor technology is scaling down to a few nanometers, aging effects such as Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) are increasing which worsens the reliability. Scaling down the transistor size along with the supply voltage increases the susceptibility of NoC to soft errors. Faults and disturbances due to aging and voltage scaling cause serious degradation in reliability of NoC. In this thesis, I propose RETUNES - Reliable and energy-efficient NoC design, where power efficient and fault-tolerant architecture is modeled without compromising on the performance of NoC. The energy-efficient part of RETUNES is a five voltage/frequency design that includes NTV for high energy gains. The five voltage modes are switched according to the workload for high energy-efficiency and minimum network congestion in NoC. Energy efficiency of RETUNES is further improved by employing approximate communication throughout the execution of the application within the tolerable error range. The reliability part of RETUNES introduces a hybrid error correction model to handle the faults observed due to aging, voltage scaling, and temperature. In addition to error correction and detectio

关键词： Electrical Engineering Network-on-Chip Energy efficiency Reliability Aging adaptive routing algorithm Approximate communication Near Threshold Voltage NBTI HCI

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Minimizing the system impact of router faults by means of reconfiguration and adaptive routing

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MICROPROCESSORS AND MICROSYSTEMS 2017年 51卷 252-263页

作者： Wang, Junshi Ebrahimi, Masoumeh Huang, Letian Li, Qiang Li, Guangjun Jantsch, Axel Vienna Univ Technol Vienna Austria Univ Elect Sci & Technol China Chengdu Sichuan Peoples R China Royal Inst Technol Stockholm Sweden Univ Turku Turku Finland Vienna Univ Technol Inst Comp Technol Vienna Austria

To tolerate faults in Networks-on-Chip (NoC), routers are often disconnected from the NoC, which affects the system integrity. This is because cores connected to the disabled routers cannot be accessed from the network, resulting in loss of function and performance. We propose E-Rescuer, a technique offering a re configurable router architecture and a fault-tolerant routing algorithm. By taking advantage of bypassing channels, the reconfigurable router architecture maintains the connection between the cores and the network regardless of the router status. The routing algorithm allows the core to access the network when the local router is disabled. Our analysis and experiments show that the proposed technique provides 100% packet delivery in 100%, 92.56%, and 83.25% of patterns when 1, 2 and 3 routers are faulty, respectively. Moreover, the throughput increases up to 80%, 46% and 33% in comparison with FTLR, HiPFaR, and CoreRescuer, respectively. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Reconfigurable router architecture Bypassing channels adaptive routing algorithm

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CAP-W: Congestion-aware platform for wireless-based network-on-chip in many-core era

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MICROPROCESSORS AND MICROSYSTEMS 2017年 52卷 23-33页

作者： Rezaei, Amin Daneshtalab, Masoud Zhao, Dan Northwestern Univ Dept Elect Engn & Comp Sci Evanston IL 60208 USA Royal Inst Technol KTH Dept Elect Syst Stockholm Sweden Old Dominion Univ Dept Comp Sci Norfolk VA 23529 USA

In order to fulfill the ever-increasing demand for high-speed and high-bandwidth, wireless-based MCSoC is presented based on a NoC communication infrastructure. Inspiring the separation between the communication and the computation demands as well as providing the flexible topology configurations, makes wireless-based NoC a promising future MCSoC architecture. However, congestion occurrence in wireless routers reduces the benefit of high-speed wireless links and significantly increases the network latency. Therefore, in this paper, a congestion-aware platform, named CAP-W, is introduced for wireless-based NoC in order to reduce congestion in the network and especially over wireless routers. The triple-layer platform of CAP-W is composed of mapping, migration, and routing layers. In order to minimize the congestion probability, the mapping layer is responsible for selecting the suitable free core as the first candidate, finding the suitable first task to be mapped onto the selected core, and allocating other tasks with respect to contiguity. Considering dynamic variation of application behaviors, the migration layer modifies the primary task mapping to improve congestion situation. Furthermore, the routing layer balances utilization of wired and wireless networks by separating short-distance and long-distance communications. Experimental results show meaningful gain in congestion control of wireless-based NoC compared to state-of-the-art works. (C) 2017 Elsevier B.V. All rights reserved.

关键词： Network-on-Chip Wireless Network-on-Chip Congestion Dynamic Application Mapping Dynamic Task Migration adaptive routing algorithm

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