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Silica-Embedded Silicon Nanophotonic On-Chip Networks

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2017年第6期36卷 978-991页

作者： Kakoulli, Elena Soteriou, Vassos Koutsides, Charalambos Kalli, Kyriacos Cyprus Univ Technol Dept Elect Engn Comp Engn & Informat CY-3036 Limassol Cyprus

On-chip nanophotonics offer high throughput, yet energy-efficient communication, traits that can prove critical to the continuance of multicore chip scalability. In this paper, we investigate and propose silicon nanophotonic components that are embedded entirely in the silica (SiO2) substrate, i.e., reside subsurface, as opposed to die on-surface silicon nanophotonics of prior-art. Among several offered advantages, such silicon-in-silica (SiS) nanophotonic structures empower the implementation of nonobstructive interconnect geometries that deliver an improved power-performance balance, as demonstrated experimentally. First, using exhaustive simulations based on commercial-grade optical software-based tools, we show that such SiS structures are feasible, and derive their geometry characteristics and design parameters. As a second step, utilizing SiS optical channels and filters, we then design two distinct SiS-based nanophotonic network-on-chip (PNoC) mesh-diagonal links topologies as a means of demonstrating our proof of concept. In further pushing the performance envelope, we next develop: 1) an associated contention-aware adaptive routing function and 2) a parallelized photonic channel allocation scheme, with both coupled to SiS-based PNoCs as elements, to respectively replace under-performing routing and flow-control photonic protocols currently utilized. An extensive experimental evaluation, including utilizing traffic benchmarks gathered from full-system chip multiprocessor simulations, shows that our methodology boosts network throughput by up to 59.7%, reduces communication latency by up to 78.7%, while improving the throughput-to-power ratio by up to 31.6% when compared to the state-of-the-art.

关键词： adaptive routing algorithm flow-control nanophotonic network-on-chip (PNoC) silicon-in-silica (SiS) topology

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Efficient Regional Congestion Awareness(ERCA) for Load Balance with Aggregated Congestion Information 25

Efficient Regional Congestion Awareness(ERCA) for Load Balan...

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25th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP)

作者： Xu, Sheng Wu, Jie Fu, Binzhang Chen, Mingyu Zhang, Lixin Chinese Acad Sci ICT State Key Lab Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9781509060580

In this paper, we propose Efficient Regional Congestion Awareness(ERCA), a novel adaptive routing technique which utilizes both local and non-local/aggregated congestion information to estimate network congestion. To reduce the interference caused by the noises of the congestion information, two optimizations are performed: first, to minimize the noises of the congestion information, ERCA only considers the congestion status of the links adjacent to the nodes defined from current to the corresponding boundary;second, to minimize the influence of the noises, ERCA exploits dynamic instead of static weights to evaluate port's congestion. Furthermore, ERCA uses one wire per dimension direction or quadrant to transmit congestion information between two adjacent nodes, so the wiring overhead of ERCA is minimal. Compared with the DBAR, ERCA can maximally improve the saturation throughput by 11.7% and averagely improve the saturation throughput by 6.02%.

关键词： Network-on-Chip regional congestion awareness adaptive routing algorithm

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AdapNoC: A Fast and Flexible FPGA-based NoC Simulator 26

AdapNoC: A Fast and Flexible FPGA-based NoC Simulator

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26th International Conference on Field-Programmable Logic and Applications (FPL)

作者： Kamali, Hadi Mardani Hessabi, Shahin Sharif Univ Technol Dept Comp Engn Tehran Iran

ISBN: (纸本)9782839918442

Network on Chip (NoC) is the most common interconnection platform for multiprocessor systems-on-chips (MPSoCs). In order to explore the design space of this platform, we need a high-speed, cycle-accurate, and flexible simulation tool. In this paper, we present AdapNoC, a configurable cycle-accurate FPGA-based NoC simulator, which can be configured via software. A wide range of parameters are configurable in FPGA side of the proposed simulator, and the software side is implemented on an embedded soft-core processor. We transfer some parts of simulator, such as Traffic Generators (TGs) and Traffic Receptors (TRs), to software side without any degradation in simulation speed. Moreover, we implement a dual-clock architecture as an innovation in virtualization methodology, which is also capable to share idle time-slots, which helps not only simulate bigger NoCs, but also reduce simulation time drastically. Also, by employing a traffic aggregator architecture, AdapNoC provides table-based adaptive routing algorithm as a configurable parameter in router microarchitecture. We evaluate simulation time of AdapNoC by using Xilinx Virtex-6 XC6VLX240T, and demonstrate 53x-180x speed-up against BOOKSIM. Also, due to our proposed virtualization, and TGs and TRs migration to software side, we can implement a 64-node non-virtualized or a 1024-node virtualized mesh network in only %72 of Xilinx Virtex-6 XC6VLX240T resources.

关键词： NoC FPGA adaptive routing algorithm virtualization Dual-Clock

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Router Architecture for the Interconnection Network: A Review 2

Router Architecture for the Interconnection Network: A Revie...

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2nd International Conference on Computing, Communication, Control and Automation (ICCUBEA)

作者： Kayarkar, Ashish V. Khurge, Deepti S. Pimpri Chinchwad Coll Engn Pune Maharashtra India

ISBN: (纸本)9781509032914

High performance computing are useful in performing colossal amount of computation. Interconnect network is crucial when such a tremendous calculation is happening. In order to perform high speed computation, nodes in the system must be connected with a high speed interconnection network. HPC systems have computation and communication parts and performance is limited by communication network rather than computation network. Topology, routing, and flow control are design parameters for interconnect network. routing algorithm helps the packet to move from source to destination. Router is the key element in implementing adaptive routing algorithm on hardware as it forwards packet from source node to destination through multiple hops. Scheduler and routing controller are responsible for actually forwarding packets based on routing algorithm. The important parameter considered while designing router is a switching technique. There are number of router architecture proposed earlier with switching techniques such as VCT and wormhole. This paper compares previous routers and describes the design of the router used for implementation of the adaptive algorithm on FPGA for 3D Torus. This router uses credit based flow control and Virtual cut through s witching technique.

关键词： High-performance computing routing algorithm adaptive routing algorithm Torus router virtual channels

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Towards High Performance Network-on-Chip: A Survey on Enabling Technologies, Open Issues and Challenges 3

Towards High Performance Network-on-Chip: A Survey on Enabli...

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3rd International Conference on Electronic Design (ICED)

作者： Phing, Ng Yen Warip, M. N. Mohd Ehkan, Phaklen Ahmad, R. Badlishah Zakaria, Fazrul Faiz Zulkefli, Farah Wahida Univ Malaysia Perlis Sch Comp & Commun Engn Embedded Network & Adv Comp Res Cluster Arau Perlis Malaysia

ISBN: (纸本)9781509021604

One of the greatest challenges with cutting edge technology in System-on-Chip (SoC) is capability of processing core especially for complex and larger network size interconnections. Additionally, it is important to consider the effectiveness of routing algorithm in the overall performance of Network-on-Chip (NoC). Hence, the design and implementation of networks-on-chip should be considering aspects of simplicity in design, bandwidth usage, delay and power consumption. In essence, adaptive technique is a potential routing algorithm for better performance in network-on-chip (NoC) in which have properties such as prevention of livelock, deadlock, and starvation. This paper employed survey to investigate the impact of deterministic routing algorithm that has degrade overall performance and deadlock happen due to the fixed direction to the destination. An adaptive routing algorithm straighten out the problem of deadlock from deterministic routing algorithm by providing routing flexibility.

关键词： adaptive routing algorithm Odd-Even (OE) routing algorithm DyAD routing algorithm NoC routing XY routing algorithm

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A Multipath Network-on-Chip Topology

A Multipath Network-on-Chip Topology

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International Conference on Information Communication and Embedded Systems (ICICES)

作者： Ray, Kaushik Kalita, Alakesh Biswas, Abhijit Hussain, Md. Anwar Assam Univ Dept Informat Technol Silchar Assam India NERIST Dept Elect & Commun Engn Nirjuli Arunachal Prade India

ISBN: (纸本)9781509025527

Network-on-Chip (NoC) is a new on chip communication design system that replaced bus-based communication in System-on-Chip (SoC). It provides efficient and scalable communication among the IPs (Intellectual Properties) in a single chip. Mainly, it was introduced to fulfill the growing demand of electronics system which needs to integrate a large number of computational resources into a single chip with an aim to get high performances, And to get efficient performance, the interconnection network plays an important role in chip design. The network architecture or topology should be highly scalable so that it can incorporate a large number of IPs without degrading the performance. In this paper, we proposed a network topology that provides multiple path diversity and high degree of scalability. The architecture of the proposed topology is described along with a packet based adaptive routing algorithm. We simulated the network using an open source simulator named OMNeT++. The topology is tested for average latency, number of events that to be carried in the simulation using a packet based routing algorithm and has been compared with existing Fat tree topology.

关键词： Network-On-Chip (NoC) System-on-Chip (SoC) intellectual properties topology packet switch adaptive routing algorithm

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The Design and Implementation of A NoC System Based on SoCKit

The Design and Implementation of A NoC System Based on SoCKi...

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International Conference on Networking and Network Applications (NaNA)

作者： Ye, Hongwei Wang, Quan Yang, Pengfei Li, Wei Yu, Zhibin Xidian Univ Inst Comp Xian Peoples R China

ISBN: (纸本)9781467398039

With the further increase in integration density, the network-based highly parallel System on Chip (SoC) has evolved as a promising on-chip interconnect for future Chip Multi-Processors (CMPs). The high performance SOC platform is quite serviceable for MPSoC research. In this paper, we built a typical NoC (Network on-chip) system on SoCKit, and designed the hardware and software of the system which based on the previous theory research on NoC including fault tolerant topology, adaptive routing algorithm, task scheduling and mapping. The system function is verified by running a halftone algorithm.

关键词： SOC-FPGA Network-on-Chip Fault Tolerance adaptive routing algorithm Task Scheduling

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Efficient Congestion-Aware Scheme for Wireless On-Chip Networks 24

Efficient Congestion-Aware Scheme for Wireless On-Chip Netwo...

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24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

作者： Rezaei, Amin Daneshtalab, Masoud Palesi, Maurizio Zhao, Danella Univ Louisiana Lafayette Lafayette LA 70504 USA KTH Royal Inst Technol Stockholm Sweden Kore Univ Enna Italy

ISBN: (纸本)9781467387767

Wireless NoC is becoming popular to be a promising future on-chip interconnection network as a result of high bandwidth, low latency and flexible topology configurations provided by this emerging technology. Nonetheless, congestion occurrence in wireless routers negatively affects the usability of high speed wireless links and considerably increases the network latency;therefore, in this paper, a congestion-aware platform (CAP-W) is introduced for wireless NoCs in order to reduce both internal and external congestions. The whole platform of CAP-W consists of an adaptive routing algorithm that balances utilization of wired and wireless networks, a dynamic task mapping approach that tries to minimize congestion probability, and a task migration strategy that considers dynamic variation of application behaviors. Simulation results show significant gain in congestion control over PEs of wireless NoC, compared to state-of-the-art works.

关键词： Network-on-Chip Wireless Network-on-Chip Congestion Dynamic Application Mapping adaptive routing algorithm Task Migration

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An adaptive routing algorithm Over Packet Switching Networks for Operation Monitoring of Power Transmission Systems

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IEEE TRANSACTIONS ON POWER DELIVERY 2010年第2期25卷 882-890页

作者： Chuang, Cheng-Long Wang, Yung-Chung Lee, Chien-Hsing Liu, Maw-Yang Hsiao, Ying-Tung Jiang, Joe-Air Natl Taiwan Univ Dept Bioind Mechatron Engn Taipei 106 Taiwan Natl Taiwan Univ Inst Biomed Engn Taipei 106 Taiwan Natl Taipei Univ Technol Dept Elect Engn Taipei 106 Taiwan Natl Cheng Kung Univ Dept Syst & Naval Mechatron Engn Tainan 701 Taiwan Natl Ilan Univ Dept Elect Engn Ilan 260 Taiwan Natl Taipei Univ Educ Dept Comp Sci Taipei 106 Taiwan

This paper reports on the development and subsequent use of a packet switching communication model for monitoring of power transmission line systems. Modern fault detection and fault location techniques for EHV/UHV transmission networks usually work based on the data measured by a phasor measurement unit (PMU). Digital cameras have also been widely utilized to monitor the physical status of power transmission lines on electricity pylons. PMU measures voltage and current phasors with synchronized time stamps, and then transmits the measured data to a monitoring center for analysis. The transmission of these data is required to be very stable. For the sake of operation speed and system security, the development of an enhanced communication infrastructure that guarantees the quality of service (QoS) for the essential measured data is a crucial issue. We have developed an adaptive routing algorithm for packet switching networks to guarantee the QoS of important power system communications and have conducted computer simulations to demonstrate the effectiveness of the proposed algorithm. The proposed algorithm can minimize transmission delay and reduce the number of redundant transmissions caused by loss of packets. Hence, the simulation results show the feasibility of packet switching networks on monitoring power systems.

关键词： adaptive routing algorithm network fault tolerance packet switching network power transmission system QoS

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adaptive Look Ahead algorithm for 2-D Mesh NoC 5

Adaptive Look Ahead Algorithm for 2-D Mesh NoC

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IEEE International Advance Computing Conference (IACC 2015)

作者： Menon, Abhilash Zeng, Lian Jiang, Xin Watanabe, Takahiro Waseda Univ Grad Sch IPS ASIC Design Automat Lab Kitakyushu Fukuoka Japan

ISBN: (纸本)9781479980475

The existing System on Chip (SoC) design will soon become a critical bottle neck in chip performance with its inability to scale its communication network effectively with decreasing feature sizes and increasing number of transistors. The Network on Chip (NoC) has been recognized as the next evolutionary step to tackle these issues by using an intelligent and common communication network between all the different components within chip. In this paper we propose a new routing algorithm that uses a combination of a fully adaptive and partial adaptive routing algorithm called adaptive Look Ahead algorithm. The algorithm decides next two hops within one node to allow quick packet transfer in next node, hence the algorithm only periodically calculates the packets route along the minimal path. Experimental results show that our proposed algorithm has lower latency and higher throughput than existing benchmarks.

关键词： 2-D mesh NoC adaptive routing algorithm look ahead routing algorithm

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