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Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal adaptive routing

IEEE TRANSACTIONS ON COMPUTERS 2014年第3期63卷 718-733页

作者： Ebrahimi, Masoumeh Daneshtalab, Masoud Liljeberg, Pasi Plosila, Juha Flich, Jose Tenhunen, Hannu Univ Turku Dept Informat Technol FIN-20520 Turku Finland Univ Politecn Valencia Escuela Tecn Super Ingn Informat Dept Informat Sistemas & Comp E-46071 Valencia Spain

Combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain in Chip Multiprocessors (CMPs) architectures. As multicast communication is commonly used in cache coherence protocols for CMPs and in various parallel applications, the performance of these systems can be significantly improved if multicast operations are supported at the hardware level. In this paper, we present several partitioning methods for the path-based multicast approach in 3D mesh-based NoCs, each with different levels of efficiency. In addition, we develop novel analytical models for unicast and multicast traffic to explore the efficiency of each approach. In order to distribute the unicast and multicast traffic more efficiently over the network, we propose the Minimal and adaptive routing (MAR) algorithm for the presented partitioning methods. The analytical and experimental results show that an advantageous method named Recursive Partitioning (RP) outperforms the other approaches. RP recursively partitions the network until all partitions contain a comparable number of switches and thus the multicast traffic is equally distributed among several subsets and the network latency is considerably decreased. The simulation results reveal that the RP method can achieve performance improvement across all workloads while performance can be further improved by utilizing the MAR algorithm. Nineteen percent average and 42 percent maximum latency reduction are obtained on SPLASH-2 and PARSEC benchmarks running on a 64-core CMP.

关键词： 3D Networks-on-Chip unicast and multicast communication partitioning methods analytical models adaptive routing algorithm

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Holistic routing algorithm Design to Support Workload Consolidation in NoCs

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IEEE TRANSACTIONS ON COMPUTERS 2014年第3期63卷 529-542页

作者： Ma, Sheng Jerger, Natalie Enright Wang, Zhiying Lai, Mingche Huang, Libo Natl Univ Def Technol Sch Comp Changsha 410073 Hunan Peoples R China Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

To provide efficient, high-performance routing algorithms, a holistic approach should be taken. The key aspects of routing algorithm design include adaptivity, path selection strategy, VC allocation, isolation, and hardware implementation cost;these design aspects are not independent. The key contribution of this work lies in the design of a novel selection strategy, Destination-Based Selection Strategy (DBSS), which targets interference that can arise in many-core systems running consolidation workloads. In the process of this design, we holistically consider all aspects to ensure an efficient design. Existing routing algorithms largely overlook issues associated with workload consolidation. Locally adaptive algorithms do not consider enough status information to avoid network congestion. Globally adaptive routing algorithms attack this issue by utilizing network status beyond neighboring nodes. However, they may suffer from interference, coupling the behavior of otherwise independent applications. To address these issues, DBSS leverages both local and nonlocal network status to provide more effective adaptivity. More importantly, by integrating the destination into the selection procedure, DBSS mitigates interference and offers dynamic isolation among applications. Results show that DBSS offers better performance than the best baseline selection strategy and improves the energy-delay product for medium and high injection rates;it is well suited for workload consolidation.

关键词： Networks-on-chip adaptive routing algorithm workload consolidation

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adaptive load balancing in learning-based approaches for many-core embedded systems

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JOURNAL OF SUPERCOMPUTING 2014年第3期68卷 1214-1234页

作者： Farahnakian, F. Ebrahimi, M. Daneshtalab, M. Liljeberg, P. Plosila, J. Univ Turku Turku Finland

adaptive routing algorithms improve network performance by distributing traffic over the whole network. However, they require congestion information to facilitate load balancing. To provide local and global congestion information, we propose a learning method based on dual reinforcement learning approach. This information can be dynamically updated according to the changing traffic condition in the network by propagating data and learning packets. We utilize a congestion detection method which updates the learning rate according to the congestion level. This method calculates the average number of free buffer slots in each switch at specific time intervals and compares it with maximum and minimum values. Based on the comparison result, the learning rate sets to a value between 0 and 1. If a switch gets congested, the learning rate is set to a high value, meaning that the global information is more important than local. In contrast, local is more emphasized than global information in non-congested switches. Results show that the proposed approach achieves a significant performance improvement over the traditional Q-routing, DRQ-routing, DBAR and Dynamic XY algorithms.

关键词： Congestion-aware routing algorithm adaptive routing algorithm Q-learning and Q-routing approaches

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High-Performance and Fault-Tolerant 3D NoC-Bus Hybrid Architecture Using ARB-NET-Based adaptive Monitoring Platform

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IEEE TRANSACTIONS ON COMPUTERS 2014年第3期63卷 734-747页

作者： Rahmani, Amir-Mohammad Vaddina, Kameswar Rao Latif, Khalid Liljeberg, Pasi Plosila, Juha Tenhunen, Hannu Univ Turku Dept Informat Technol Embedded Comp & Elect Syst Lab FIN-20520 Turku Finland Turku Ctr Comp Sci Turku 20520 Finland

The emerging three-dimensional integrated circuits (3D-ICs) achieve greater device integration and enhanced system performance at lower cost and reduced area footprint, thereby offering higher order of connectivity and greater design choices and possibilities. To exploit the intrinsic capability of reduced communication distances in 3D-ICs, three-dimensional NoC-bus hybrid mesh architecture was proposed. Besides its various advantages in terms of area, power consumption, and performance, this architecture has a unique and hitherto previously unexplored possibility to implement an efficient system-wide monitoring network. In this paper, an efficient three-dimensional NoC architecture is proposed which is optimized for system performance, power consumption, and reliability. The mechanism benefits from a congestion-aware and bus failure-tolerant routing algorithm called adaptiveZ for vertical communication. In addition, we have integrated a low-cost monitoring platform on top of the three-dimensional NoC-Bus Hybrid mesh architecture that can be efficiently used for various system management purposes such as traffic monitoring, fault tolerance, and thermal management. The proposed generic monitoring platform called ARB-NET utilizes bus arbiters to exchange the monitoring information directly with each other without using the data network. As a test case, based on the proposed monitoring platform, a fully congestion-aware and interlayer fault-tolerant routing algorithm named adaptiveXYZ is presented taking advantage of information generated within bus arbiters. Compared to recently proposed stacked mesh three-dimensional NoCs, our extensive simulations with synthetic and real benchmarks reveal that our architecture using the adaptiveXYZ routing can help in achieving significant power, performance, and reliability improvements with a negligible hardware overhead.

关键词： Three-dimensional NoC-bus hybrid architecture monitoring platform adaptive routing algorithm three-dimensional ICs fault tolerance

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Bi-LCQ: A low-weight clustering-based Q-learning approach for NoCs

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MICROPROCESSORS AND MICROSYSTEMS 2014年第1期38卷 64-75页

作者： Farahnakian, F. Ebrahimi, M. Daneshtalab, M. Liljeberg, P. Plosila, J. Univ Turku Dept Informat Technol Turku Finland

Network congestion has a negative impact on the performance of on-chip networks due to the increased packet latency. Many congestion-aware routing algorithms have been developed to alleviate traffic congestion over the network. In this paper, we propose a congestion-aware routing algorithm based on the Q-learning approach for avoiding congested areas in the network. By using the learning method, local and global congestion information of the network is provided for each switch. This information can be dynamically updated, when a switch receives a packet. However, Q-learning approach suffers from high area overhead in NoCs due to the need for a large routing table in each switch. In order to reduce the area overhead, we also present a clustering approach that decreases the number of routing tables by the factor of 4. Results show that the proposed approach achieves a significant performance improvement over the traditional Q-learning, C-routing, DBAR and Dynamic XY algorithms. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Network-on-Chip Congestion-aware routing algorithm adaptive routing algorithm Q-learning and Q-routing approaches

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Optimized and Dependable Router suitable for Dynamic Networks on Chip

Optimized and Dependable Router suitable for Dynamic Network...

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2nd International Conference on Control, Decision and Information Technologies (CoDIT)

作者： Frihi, M. Boutalbi, M. Toumi, S. Tanougast, C. Heil, M. Univ Badji Mokhtar LERICA Annaba Algeria Univ Lorraine Metz France

ISBN: (纸本)9781479967735

This paper proposes an optimize dependable router suitable for accurate online error detections in adaptive or dynamic Networks on Chip (NoC). The proposed router detects and localizes data packet errors in the networks based on adaptive routing algorithm. The main originality of the proposed router is its capability to distinguish temporary and permanently errors through specific error detection mechanisms. In this paper, the proposed and interconnected dependable switches are detailed while showing the feasibility and efficiency thanks to simulations online detection cases, and performance evaluations through Virtex VI FPGA implementation.

关键词： circuit optimisation electronic engineering computing error detection field programmable gate arrays integrated circuit testing network routing network-on-chip switches NoC Virtex VI FPGA implementation adaptive routing algorithm data packet errors error detection mechanisms interconnected dependable switches networks on chip online error detections router Field programmable gate arrays Heuristic algorithms Ports (Computers) Registers Reliability routing Table lookup

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Design and evaluation of a high throughput robust router for network-on-chip

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IET COMPUTERS AND DIGITAL TECHNIQUES 2012年第3期6卷 173-179页

作者： Alhussien, A. Wang, C. Bagherzadeh, N. Univ Calif Irvine Dept Elect Engn & Comp Engn Irvine CA 92697 USA

Network-on-chip (NoC) systems have been proposed to achieve high-performance computing where multiple processors are integrated into one chip. As the number of cores increases and the chips are scaled in the deep submicron technology, the NoC systems become subject to physical manufacture defects and running-time vulnerability, which result in faults. The faults affect the performance and functionality of the NoC systems and result in communication malfunctions. In this study, a fault tolerant router design with an adaptive routing algorithm that tolerates faults in the network links and the router components is proposed. The approach does not require the use of virtual channels and assures deadlock freedom. Furthermore, the experimental results show that the proposed architecture can tolerate multiple failures and prove robustness and fault tolerance with negligible impact on the performance.

关键词： Network-on-chip multiple processors Communication network design, planning and routing adaptive routing algorithm router components fault tolerant router design running-time vulnerability network-on-chip systems high-performance computing telecommunication network routing high throughput robust router virtual channels NoC systems network links fault tolerance deadlock freedom deep submicron technology network-on-chip manufacture defects

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Optimized Q-learning Model for Distributing Traffic in On-Chip Networks

Optimized Q-learning Model for Distributing Traffic in On-Ch...

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IEEE 3rd International Conference on Networked Embedded Systems for Every Application (NESEA)

作者： Farahnakian, Fahimeh Ebrahimi, Masoumeh Daneshtalab, Masoud Plosila, Juha Liljeberg, Pasi Univ Turku Dept Informat Technol Turku Finland

ISBN: (纸本)9781467347211

Many adaptive routing protocols have been developed for Networks -on-Chip to improve the network performance by traffic reduction. In this paper, we present an adaptive routing algorithm based upon the Q-routing, which distributes traffic by a learning method in the entire network. The learning method utilizes local and global traffic information and can select the minimum latency path to the destination. Since the routing table sizes become one of the main sources of area consumption in the Q-routing algorithm, we propose a clustering approach in order to reduce the area overhead. Furthermore, this approach improves the observability of the traffic condition. Experimental results for different traffic patterns and network loads show that the proposed method achieves significant performance improvement over the Q-routing, C-routing, DBAR and Dynamic XY algorithms.

关键词： Network-on-Chip adaptive routing algorithm Congestion-aware routing algorithm Q-routing

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A novel globally adaptive load-balanced routing algorithm for torus interconnection networks

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ETRI JOURNAL 2007年第3期29卷 405-407页

作者： Wang, Hong Xu, Du Li, Lemin Univ Elect Sci & Technol China Key Lab Broadband & Opt Commun Chengdu 610054 Peoples R China

A globally adaptive load-balanced routing algorithm for torus interconnection networks is proposed. Unlike previously published algorithms, this algorithm employs a new scheme based on collision detection to handle deadlock;and has higher routing adaptability than previous algorithm. Simulation results show that our algorithm outperforms previous algorithms by 16% on benign traffic patterns, and by 10% to 21% on adversarial traffic patterns.

关键词： Torus interconnection network adaptive routing algorithm load-balance traffic pattem deadlock

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Performance evaluation of fully adaptive routing for the torus interconnect networks

Performance evaluation of fully adaptive routing for the tor...

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7th International Conference on Computational Science (ICCS 2007)

作者： Safaei, F. Khonsari, A. Fathy, M. Ould-Khaoua, M. IPM Sch Comp Sci Tehran Iran Univ Tehran Dept ECE Tehran Iran Iran Univ Sci & Technol Dept Comp Eng Tehran Iran Univ Glasgow Dept Comp Sci Glasgow Lanark Scotland

ISBN: (纸本)9783540725893

adaptive routing algorithms have been frequently suggested as a means of improving communication performance in parallel computer networks. These algorithms, unlike deterministic routing, can utilize network state information to exploit the presence of multiple paths. Before such schemes can be successfully incorporated in networks, it is necessary to have a clear understanding of the factors which affect their performance potential. This paper proposes a new analytical model to obtain message latency in wormhole-switched 2-D torus interconnect networks. The analysis focuses on a fully adaptive routing which has been shown to be one of the most effective in torus networks. The validity of the model is demonstrated by comparing analytical results with those obtained through simulation experiments.

关键词： adaptive routing algorithm parallel computer network torus Interconnect-Networks

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