Error detection and correction (EDAC) functions have been widely used for protecting memories from single event upsets (SEU), which occur in environments with high levels of radiation or in deep submicron manufacturin...
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Error detection and correction (EDAC) functions have been widely used for protecting memories from single event upsets (SEU), which occur in environments with high levels of radiation or in deep submicron manufacturing technologies. This paper presents three novel synthesis algorithms that obtain area-efficient implementations for a given EDAC function, with the ultimate aim of reducing the number of sensitive configuration bits in SRAM-based field-programmable gate arrays (FPGAs). Having less sensitive bits results in a lower chance of suffering an SEU in the EDAC circuitry, thus improving the overall reliability of the whole system. Besides minimizing area, the proposed algorithms also focus on improving other figures of merit like circuit speed and power consumption. The executed benchmarks show that, when compared with other modern synthesis tools, the proposed algorithms can reduce the number of utilized look-up tables (LUTs) up to a 34.48%. Such large reductions in area usage ultimately result in reliability improvements over 10% for the implemented EDAC cores, measured as MTBF (mean time between failures). On the other hand, maximum path delays and power consumptions can be reduced up to a 17.72% and 34.37%, respectively, on the placed and routed designs.
FPGA's combine the logic integration benefits of custom VLSI with the design, production, and time-to-market advantages of standard logic IC's. The Actel family of FPGA's exemplifies the row-based FPGA mod...
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FPGA's combine the logic integration benefits of custom VLSI with the design, production, and time-to-market advantages of standard logic IC's. The Actel family of FPGA's exemplifies the row-based FPGA model. Rows of logic cells interspersed with routing channels have given this family of FPGA devices the flavor of traditional channeled gate arrays or standard cells. However, unlike the conventional standard cell design, the FPGA routing channels contain predefined wiring segments of various lengths that are interconnected using antifuses. This paper develops analytical models that permit the design of FPGA channel architecture and the analysis of the routability of row-based FPGA devices based on a generic characterization of the row-based FPGA routing algorithms. In particular, it demonstrates that using probabilistic models for the origination point and length of connections, an FPGA with properly designed segment length and distribution can be nearly as efficient as a mask-programmable channel (in terms of the number of required tracks). Experimental results corroborate this prediction. This paper does not address specifics of the routing algorithms, but investigates the design of the channel segmentation architecture (i.e, various lengths and patterns of segments and connections among these segments) in order to increase the probability of successful routing.
The paper reviews the digital AC bridge. A more accurate and thorough analysis of the bridge is presented. Based on the analysis a simple adaptive algorithm is proposed in order to ensure fast conversion. In addition,...
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The paper reviews the digital AC bridge. A more accurate and thorough analysis of the bridge is presented. Based on the analysis a simple adaptive algorithm is proposed in order to ensure fast conversion. In addition, a new design of the bridge, based on the TMS 320C25, is given. The system is implemented with the Dalanco Spry model 25 DSP board, on a software system designed whereby an IBM PC host computer provides control of the bridge. Experimental results are presented.
In this paper, we consider the problem of dynamic channel allocation in cellular networks. Each cell can use any channel, subject to the interference constraints. Channel allocation algorithms are executed by the netw...
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In this paper, we consider the problem of dynamic channel allocation in cellular networks. Each cell can use any channel, subject to the interference constraints. Channel allocation algorithms are executed by the network switch in a centralized way. We show how to design and use objective functions aimed at proper channel allocation and improvement of network performance. As a figure of merit of network performance, we consider the blocking probability in the network as a whole, and the maximum blocking probability in any particular cell of the network (''hot-spot'' in the network). We designed three specific channel allocation policies, based on three different objective functions. Compared with two other benchmark policies, our approach shows significant improvement. Performance analysis of various channel allocation policies is virtually impossible without simulations, which are prohibitively time-consuming in the case of small blocking probabilities. We propose an original approximate method based on a short simulation and an analytic approximation. The method exhibits good accuracy and significant improvement in efficiency.
In this paper, we examine the performance of uniform backoff (UB) and binary exponential backoff (BEB) algorithms with retry limit, which can be used in the random-access channels of Universal Mobile Telecommunication...
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In this paper, we examine the performance of uniform backoff (UB) and binary exponential backoff (BEB) algorithms with retry limit, which can be used in the random-access channels of Universal Mobile Telecommunication System (UMTS)-Long Term Evolution (LTE) and IEEE 802.16 systems under the assumption of finite population under unsaturated traffic conditions. Additionally, we consider access prioritization schemes to provide differential performance by controlling various system parameters. We show that controlling the persistence value as specified in UMTS is effective in both backoff algorithms. The performances with and without access prioritization schemes are presented in terms of throughput, mean, and variance of packet retransmission delay, packet-dropping probability, and system stability. Finally, we consider a dynamic window assignment algorithm that is based on Bayesian broadcasting, in which the base station adaptively controls the window size of the UB algorithm under unsaturated traffic conditions. Results show that the proposed window assignment algorithm outperforms fixed window assignment in static and dynamic traffic conditions under the assumption of perfect orthogonality between random-access codes.
This paper presents an effective designalgorithm for analysis-synthesis filter banks with computationally efficient structures. Although a wide variety of implementation structures can be accommodated, the focus of t...
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This paper presents an effective designalgorithm for analysis-synthesis filter banks with computationally efficient structures. Although a wide variety of implementation structures can be accommodated, the focus of this paper is on cosine modulated filter banks. The design procedure is based on a time domain formulation of analysis-synthesis filter banks in which each individual channel filter is constrained to be a cosine modulated versions of a baseband filter. The resulting filter banks are very efficient in terms of computational requirements and are relatively easy to design. A unique feature of this approach is that relatively low reconstruction delays can be imposed on the system. A discussion of the associated computational properties of the designed systems and some design examples are included.
A statistical model is used for the optimal design of analysis/synthesis systems that include quantization of the signals in separate bands. Two types of quantization approaches are analyzed: fine quantization modelle...
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A statistical model is used for the optimal design of analysis/synthesis systems that include quantization of the signals in separate bands. Two types of quantization approaches are analyzed: fine quantization modelled by additive noise, and matrix quantization. With proper modification, the model applies to other types of quantization approaches. Assuming that the system operates as a waveform coder, two error measures are used: a generalization of the usual statistical mean-square error (MSE) to time-varying systems, and the MSE between the outputs of the analysis of the original and reconstructed signals. The measures are shown to be equivalent. A method that is applicable to the design of optimal synthesis filters, given the analysis filters, is presented. For fine quantization, an iterative algorithm for the design of an optimal analysis/synthesis system is presented, together with its convergence properties. If no quantization is applied, the results obtained with the presented method coincide with previously reported results.< >
The state of many dynamic systems evolves subject to some equality constraints. Most existing work focuses on developing state estimation algorithms for an equality-constrained dynamic system assuming the system is gi...
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The state of many dynamic systems evolves subject to some equality constraints. Most existing work focuses on developing state estimation algorithms for an equality-constrained dynamic system assuming the system is given. How to design and analyze such a system is rarely addressed, even though it is critically important for application and performance evaluation. In this paper, we first analyze the underlying structural information of linear equality-constrained (LEC) dynamic systems through direct elimination. It is found that the process noise of such a system is state dependent in general. This means that existing formulations of such a system are quite limited. Based on the analysis, we then propose a new systematic way to design LEC systems. The key idea is to design only the unconstrained part of the system. Unlike existing system conversion-based design techniques, in our work the desired model class is given and only the distributions of the initial state and process noise need to be determined, which is comparatively easier. To handle state dependency of the process noise, a new constrained state estimation algorithm based on direct elimination is also proposed. Three examples are provided to illustrate the effectiveness of the proposed methods of analysis, design, and estimation, respectively.
This correspondence discusses the design and factorization of FIR paraunitary filter banks where several analysis filters are given. A lattice factorization-based algorithm is presented that provides complete and mini...
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This correspondence discusses the design and factorization of FIR paraunitary filter banks where several analysis filters are given. A lattice factorization-based algorithm is presented that provides complete and minimal characterization for nonlinear-phase and balanced linear-phase systems. As a result, the design problem can be formulated as an unconstrained optimization of the lattice coefficients, whereas paraunitariness and linear-phase properties are structurally guaranteed. The second presented algorithm formulates the design problem in quadratic form that provides better control on the frequency responses of the embedding solution. An unitary scaling filter designalgorithm is also presented that can be paired with the paraunitary embedding solution to design orthnormal wavelet basis with high regularity. A design example is presented.
This paper presents a sensitivity analysis for the shape design problems of 2-dimensional nonlinear magnetostatic system. In order to derive the design sensitivity, the algebraic equation resulting from the finite ele...
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This paper presents a sensitivity analysis for the shape design problems of 2-dimensional nonlinear magnetostatic system. In order to derive the design sensitivity, the algebraic equation resulting from the finite element method is exploited and the adjoint variable method is used. This algorithm is applied to the shape design problem of a quadrupole magnet which operates in the magnetic saturation region and the numerical results validate the algorithm.
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