Mobile network operators are experiencing a tremendous increase in data traffic due to the growing popularity of bandwidth-intensive video services. This challenge can be faced either by boosting the capacity of the n...
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Mobile network operators are experiencing a tremendous increase in data traffic due to the growing popularity of bandwidth-intensive video services. This challenge can be faced either by boosting the capacity of the network infrastructure, or by means of offloading traffic from the backhaul and core network and serving contents from distributed cache servers close to the users. Network operators can extend the coverage of traditional CDNs by making usage of caching locations much closer to the users than traditional CDNs. Additionally, network operators can optimize the caching and delivery of contents by exploiting the complete knowledge of their network for designing a cost-effective infrastructure able to achieve both improved user satisfaction and cost savings. This article provides thoroughly justified design principles for a highly distributed operator-owned CDN while focusing on four key aspects: the optimal location of cache servers, mechanisms for request routing, content replica placement, and content outsourcing and retrieval.
The Fortran I compiler was the first demonstration that if is possible to automatically generate efficient machine code from high-level languages. It has thus been enormously influential. This article presents a brief...
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The Fortran I compiler was the first demonstration that if is possible to automatically generate efficient machine code from high-level languages. It has thus been enormously influential. This article presents a brief description of the techniques used in the Fortran I compiler for the parsing of expressions, loop optimization, and register allocation.
This tutorial gives an introduction to novices in CPS and particularly highlights the basics of control theory with respect to automotive applications. The authors furthermore describe the "semantic g" betwe...
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This tutorial gives an introduction to novices in CPS and particularly highlights the basics of control theory with respect to automotive applications. The authors furthermore describe the "semantic g" between control models and their implementation and conclude that a new CPS-oriented design approach is required.
Vector quantizer (VQ) design is a multidimensional optimization problem in which a distortion function is minimized. The most widely used technique for designing vector quantizers is the generalized Lloyd algorithm (G...
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Vector quantizer (VQ) design is a multidimensional optimization problem in which a distortion function is minimized. The most widely used technique for designing vector quantizers is the generalized Lloyd algorithm (GLA), an iterative descent algorithm which monotonically decreases the distortion function towards a local minimum. One major drawback of the GLA, and of any descent minimization technique, is the "greedy" nature of the search, generally resulting in a nonglobal local optimum. A promising alternative to the GLA is the Kohonen learning algorithm (KLA), originally proposed for unsupervised training of neural networks. The KLA is an "on-line" algorithm where the codebook is designed while training data is arriving, and the reduction of the distortion function is not necessarily monotonic. In this paper we provide a convergence analysis for the KLA with respect to VQ optimality criteria and introduce a stochastic relaxation technique which produces the global minimum but is computationally expensive. By incorporating the principles of the stochastic approach into the KLA, a new deterministic VQ designalgorithm, called the soft competition scheme (SCS), is introduced. Experimental results are presented where the SCS consistently provided better codebooks than the GLA, even when the same computation time was used for both algorithms. The SCS may therefore prove to be a valuable alternative to the GLA for VQ design.
We present an efficient FIR filter designalgorithm that generalizes existing cascaded FIR prefilter-equalizer methods. We propose using cyclotomic polynomial ''building blocks'' to form a multiplierle...
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We present an efficient FIR filter designalgorithm that generalizes existing cascaded FIR prefilter-equalizer methods. We propose using cyclotomic polynomial ''building blocks'' to form a multiplierless prefilter with impressive stopband performance, and we provide a straightforward strategy for choosing the polynomials to match filter specifications. We then provide two options for design of the equalizer. A uniformly spaced equalizer can be optimally (L(infinity)) designed via a modified Parks-McClellan algorithm. However, we also propose a new algorithm, based on complex basis function subset selection methods, to optimally design a more efficient, nonuniformly spaced equalizer. Our techniques, which can be applied to a broad class of filter design problems, typically provide a 35%-85% reduction in the number of additions and multiplications required, with a cost of 10%-45% additional delays. Furthermore, our methods provide reduced coefficient quantization sensitivity and reduced roundoff noise.
Prior work suggests that particle swarm clustering (PSC) can be a powerful tool for solving clustering problems. This paper reviews parts of the PSC algorithm, and shows how and why a new class of algorithms is propos...
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Prior work suggests that particle swarm clustering (PSC) can be a powerful tool for solving clustering problems. This paper reviews parts of the PSC algorithm, and shows how and why a new class of algorithms is proposed in an attempt to improve the efficiency and repeatability of PSC. This new implementation is referred to as rapid centroid estimation (RCE). RCE simplifies the update rules of PSC, and greatly reduces computational complexity by enhancing the efficiency of the particle trajectories. On benchmark evaluations with an artificial dataset that has 80 dimensions and a volume of 5000, the RCE variants have iteration times of less than 0.1 s, which compares to iteration times of 2 s for PSC and modified PSC (mPSC). On UC Irvine (UCI) machine learning benchmark datasets, the RCE variants are much faster than PSC and mPSC, and produce clusters with higher purity and greatly improved optimization speeds. For example, the RCE variants are more than 100 times faster than PSC and mPSC on the UCI breast cancer dataset. It can be concluded that the RCE variants are leaner and faster than PSC and mPSC, and that the new optimization strategies also improve clustering quality and repeatability.
A graph-generating algorithm and the experimental results of a hierarchical mask-layout-compaction scheme based on a plane-sweep algorithm, a fast region-query and a space-efficient data structure called the hierarchi...
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A graph-generating algorithm and the experimental results of a hierarchical mask-layout-compaction scheme based on a plane-sweep algorithm, a fast region-query and a space-efficient data structure called the hierarchical multiple-storage quad tree are presented. For a mask-layout design, a rectangle is used as the primary element of the layout. Hence, in the hierarchical mask-compaction scheme, the graph-generating algorithm is based on the edges of rectangles rather than the central lines of symbols for the symbolic-compaction design. The plane-sweep algorithm is also called a dynamic event scheduling algorithm and can be applied to solve some other problems in the field of computational geometry and image processing. The efficiencies of the plane-sweep algorithm and the graph-generating algorithm are dependent on the region-query operations of the spatial data structure. By using the improved multiple storage quad tree as the spatial data structure in the system, the mask-layout compactor has been accomplished in a practically linear time performance in terms of the rectangles in the source layout.< >
A signal may contain information that is preserved by certain transformations of the signal, For example, the information phase-modulated signal is not altered by amplitude scaling of the signal. Many processing techn...
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A signal may contain information that is preserved by certain transformations of the signal, For example, the information phase-modulated signal is not altered by amplitude scaling of the signal. Many processing techniques have been developed to exploit such similarities. In the past, these algorithms have been developed in isolation without regard to common principles of invariance that tie them together, In this paper, similarity methods are presented as a unified method of designing processing algorithms invariant to specified transformations, These methods are based upon groups of continuous transformations known as local Lie groups and lead to a quasilinear partial differential equation. Solution of this partial differential equation specifies the form the signal processing operations must take. This form can then be applied using engineering judgment for algorithmic implementation, The paper presents an extended tutorial on Lie groups and similarity methods and quasilinear differential equations drawn from the mathematical literature, This is followed by several examples of signal processing interest that demonstrate that the similarity techniques may be applicable in certain kinds of signal processing problems.
LAGER is an integrated computer-aided design (CAD) system for algorithm-specific integrated circuit (IC) design, targeted at applications such as speech processing, image processing, telecommunications, and robot cont...
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LAGER is an integrated computer-aided design (CAD) system for algorithm-specific integrated circuit (IC) design, targeted at applications such as speech processing, image processing, telecommunications, and robot control. LAGER provides user interfaces at behavioral, structural, and physical levels and allows easy integration of new CAD tools. LAGER consists of a behavioral mapper and a silicon assembler. The behavioral mapper maps the behavior onto a parameterized structure to produce microcode and parameter values. The silicon assembler then translates the filled-out structural description into a physical layout and with the aid of simulation tools, the user can fine tune the data path by iterating this process. The silicon assembler can also be used without the behavioral mapper for high sample rate applications. A number of algorithm-specific IC's designed with LAGER have been fabricated and tested, and as examples, a robot arm controller chip and a real-time image segmentation chip will be described.
A parallel higher-order method of moments (HOMoM) with a newly developed reduced-communication, lower-upper (RCLU) decomposition solver is proposed in this article. The method uses 201,600 central processing unit (CPU...
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A parallel higher-order method of moments (HOMoM) with a newly developed reduced-communication, lower-upper (RCLU) decomposition solver is proposed in this article. The method uses 201,600 central processing unit (CPU) cores on a supercomputer located in Guangzhou, China. Our code achieves an extremely high parallel efficiency when simulating a large aircraft that has been discretized in the method-of-moments (MoM) context, using a higher-order quadrilateral patch basis, into approximately 1.06 million unknowns for the surface-current distribution. Remarkably, its solution using the classical lower-upper (LU) solver only takes roughly half an hour. In addition, a review of the in-core and out-of-core algorithms of an HOMoM is presented, with a focus on their parallel implementation. The parallel performance of the methodology is also demonstrated on some challenging applications.
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