Hypercubes, meshes and tori are well known interconnection networks for parallel computers. The sets of edges in those graphs can be partitioned to dimensions. It is wen known that the hypercube can be extended by add...
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Hypercubes, meshes and tori are well known interconnection networks for parallel computers. The sets of edges in those graphs can be partitioned to dimensions. It is wen known that the hypercube can be extended by adding a wildcard dimension resulting in a folded hypercube that has better fault-tolerant and communication capabilities. First we prove that the folded hypercube is optimal in the sense that only a single wildcard dimension can be added to the hypercube. We then investigate the idea of adding wildcard dimensions to d-dimensional meshes and tori. Using techniques from error correcting codes we construct d-dimensional meshes and tori with wildcard dimensions. Finally, we show how these constructions can be used to tolerate edge and node faults in mesh and torus networks.
The channel-tracking mode performance of the front-end (FE) processors which were developed in a companion paper [1] is determined through approximate analysis and computer simulation, A general model for the FE proce...
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The channel-tracking mode performance of the front-end (FE) processors which were developed in a companion paper [1] is determined through approximate analysis and computer simulation, A general model for the FE processing, which encompasses these representative FE's, is assumed, Previous analysis techniques are extended to include the effects of FE processing. The specific system analyzed consists of a Rayleigh-fading, diffuse multipath channel with several data pulse shapes considered, An adaptive maximum likelihood sequence estimation (MLSE) algorithm based on the per-survivor processing (PSP) technique is analyzed and compared to an algorithm based on correct symbol feedback. The results show that significant performance degradation is suffered when suboptimal FE processing is used, The limitations of the results and the models used are discussed.
We present a robust, efficient algorithm for combinational test generation using a reduction to satisfiability (SAT), The algorithm, Test Generation Using Satisfiability (TEGUS), solves a simplified test set character...
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We present a robust, efficient algorithm for combinational test generation using a reduction to satisfiability (SAT), The algorithm, Test Generation Using Satisfiability (TEGUS), solves a simplified test set characteristic equation using straightforward but powerful greedy heuristics, ordering the variables using depth-first search and selecting a variable from the next unsatisfied clause at each branching point, For difficult faults, the computation of global implications is iterated, which finds more implications than previous approaches and subsumes structural heuristics such as unique sensitization. Without random tests or fault simulation, TEGUS completes on every fault in the ISCAS networks, demonstrating its robustness, and is ten times faster for those networks which have been completed by previous algorithms, Our implementation of TEGUS can be used as a base line for comparing test generation algorithms;we present comparisons with 45 recently published algorithms. TEGUS combines the advantages of the elegant organization of SAT-based algorithms with the efficiency of structural algorithms.
In this paper, we study the convergence analysis of fractionally spaced adaptive blind equalizers. We show that based on the trivial and nontrivial nullspaces of a channel convolution matrix, all equilibria can be cla...
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In this paper, we study the convergence analysis of fractionally spaced adaptive blind equalizers. We show that based on the trivial and nontrivial nullspaces of a channel convolution matrix, all equilibria can be classified as channel dependent equilibria (CDE) or algorithm dependent equilibria (ADE). Because oversampling provides channel diversity, the nullspace of the channel convolution matrix is affected. We show that fractionally spaced equalizers (FSE's) do not possess any CDE if a length-and-zero condition is satisfied. The convergence behavior of these FSE are clearly determined by the specific choice of cost function alone. We characterize the global convergence ability of several popular algorithms simply based on their ADE. We also present an FSE implementation of the super-exponential algorithm. We show that the FSE implementation does not introduce any nonideal approximation. Simulation results are also presented to illustrate the robustness and the improved performance of FSE under the super-exponential algorithm.
An approach to fault simulation is presented in which behavioral fault models represent complex failures in VLSI designs. Errors are deliberately introduced into the description of a design that contains no faults. Th...
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An approach to fault simulation is presented in which behavioral fault models represent complex failures in VLSI designs. Errors are deliberately introduced into the description of a design that contains no faults. These errors can be fault values of variables that represent state or timing parameters, a faulty description that is substituted for part of the good description, or a combination of these. The algorithm guarantees accurate results by deferring the output assignments. The approach can also be used to detect and discard inconsistent output assignments. The algorithm has been implemented in Stanford University's Sable simulator using the Adlib behavioral modeling language.
A period-independent bound, for zero and constant-input limit cycles in fixed-point digital filters, is developed. The bound is applicable to systems of arbitrary order, provided that all nonideal operations can be co...
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A period-independent bound, for zero and constant-input limit cycles in fixed-point digital filters, is developed. The bound is applicable to systems of arbitrary order, provided that all nonideal operations can be consolidated as single nonlinear operations applied at the input to each delay element. Three common types of nonlinearity (i.e. signal quantization) are considered, and a geometric interpretation is used to substantially tighten the bound for sign-magnitude signal quantization. Analytic expressions for the reduced bound are obtained for second-order sections, and an algorithm for computing the bound is presented for higher-order sections. Several numerical examples are presented for second-order sections and compared with previously published results. Two fifth-order low-pass filters (with elliptic and Chebyshev magnitude response characteristics, respectively) and one sixth-order elliptic-bandpass-filter are considered and shown to be free of zero-input limit cycles of amplitude greater than 33.< >
In this paper, a circuit model is developed to represent the input admittance of an antenna array with a finite number of elements. This model consists of a component to represent the input admittance of an isolated a...
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In this paper, a circuit model is developed to represent the input admittance of an antenna array with a finite number of elements. This model consists of a component to represent the input admittance of an isolated antenna element and infinite shunt components with each to represent different degrees of antenna mutual coupling effects. Twersky's algorithm of multiple scattering analysis is used to illustrate the physical meaning of each circuit component. Numerical results show that good accuracy for the antenna input admittance calculation can be obtained by using this model to the second order approximation. As the array is large and sparse, a very small amount of computation can yield good accuracy, This model is shown not only to be numerically efficient compared to the full wave analysis using the moment method, but also to give physical insight into the antenna array mutual coupling mechanism, Furthermore, this model has no limitation on antenna array geometry and excitation.
We develop a systolic design-rule checker (SDRC) for rectilinear geometries. This SDRC reports all width and spacing violations. It is expected to result in a significant speed up of the design-rule check phase of chi...
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We develop a systolic design-rule checker (SDRC) for rectilinear geometries. This SDRC reports all width and spacing violations. It is expected to result in a significant speed up of the design-rule check phase of chip design.
Dynamic equations are developed in nonrecursive symbolic form for chain-structured robotic manipulators with compliant links. A program is developed in REDUCE to automate the symbolic expansion of these equations for ...
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Dynamic equations are developed in nonrecursive symbolic form for chain-structured robotic manipulators with compliant links. A program is developed in REDUCE to automate the symbolic expansion of these equations for any given chain-structured manipulator. The symbolic nonrecursive form of the dynamic model is particularly suitable for controller synthesis and real-time control implementations.
We investigate the problem of decoding digital data when soft decisions are constrained to take on values from a finite set. We propose a physically reasonable objective function for selecting the desired assignment o...
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We investigate the problem of decoding digital data when soft decisions are constrained to take on values from a finite set. We propose a physically reasonable objective function for selecting the desired assignment of metrics to the received analog signals, We develop a search algorithm for designing a table-look-up that is used by the decoder to select the appropriate intermediate metrics and show that an optimum solution exists, We provide a number of illuminating examples to elucidate our ideas and work out in detail some practical cases.
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