This paper presents an algorithm for training vector quantizers with an improved version of the Neural Gas model, and its implementation in analog circuitry. Theoretical properties of the algorithm are proven that cla...
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This paper presents an algorithm for training vector quantizers with an improved version of the Neural Gas model, and its implementation in analog circuitry. Theoretical properties of the algorithm are proven that clarify the performance of the method in terms of quantization quality, and motivate design aspects of the hardware implementation. The architecture for vector quantization training includes two chips, one for Euclidean distance computation, the other for programmable sorting of codevectors. Experimental results obtained in a real application (image coding) support both the algorithm's effectiveness and the hardware performance, which can speed up the training process by up to two orders of magnitude.
Simulation data is presented for eleven benchmark circuits to show how test pattern correlation in a scan-path design circuit adversely affects delay fault coverage, and to demonstrate that most undetected delay fault...
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Simulation data is presented for eleven benchmark circuits to show how test pattern correlation in a scan-path design circuit adversely affects delay fault coverage, and to demonstrate that most undetected delay faults caused by correlation of test patterns are close to the outputs of latches. Topology- based latch correlation measures are introduced and used by a companion latch arrangement algorithm to guide the placement of latches in a scan-path design, with the objective of minimizing the effect of correlation and maximizing the coverage of delay faults. Simulation results with benchmark circuits indicate that the scan-path found by the algorithm clearly achieves better delay fault coverage than a scan-path having no deliberate arrangement. The data also indicates that the algorithm is most effective in covering delay faults that are located nearest the latch outputs of the circuit. The approach has an advantage over other arrangement schemes in that it is simple to implement and does not require significant computational time even for large circuits.
A novel recursive aggregation algorithm for numerical simulations of dynamic systems is proposed and analyzed. The algorithm exploits a special structure of the linear equation problem resulting from the discretizatio...
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A novel recursive aggregation algorithm for numerical simulations of dynamic systems is proposed and analyzed. The algorithm exploits a special structure of the linear equation problem resulting from the discretization of the dynamic system and an aggregation/disaggregation procedure. The algorithm has a time complexity of (I(q) + 2M(q) + 3) log N for solving linear systems with q states for N discrete time instants, using O(q3 N) processors, where I(q) is the parallel time complexity for inverting a q x q matrix, M(q) is the parallel time complexity for matrix multiplication of two q x q matrices. The competing parallel cyclic reduction method for the same problem has a time complexity of (I(q) + 3M(q) + 4) log N. Thus, the proposed algorithm has a definite speed advantage over the cyclic reduction method. An approximation technique for the unknown boundary conditions in boundary value problems is also proposed. The algorithm was implemented to simulate some dynamical (stable and unstable) systems, and the numerical results show that the accumulation of roundoff errors is insignificant as compared to the discretization errors.
This paper describes an analysis of track initiation performance in very high target density environments. The analysis of tracking performance performed in 161 yielded very simple expressions to predict average track...
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This paper describes an analysis of track initiation performance in very high target density environments. The analysis of tracking performance performed in 161 yielded very simple expressions to predict average track purity in terms of tracking parameters. These results were, however, obtained mainly for the track continuation phase in which tracks are more or less well established. We extend these results to the track initiation phase.
A new gain-varying algorithm for the three-dimensional pure proportional navigation (PPN) guidance problem is presented using the differential geometric (DG) guidance command. To this end, classical differential geome...
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A new gain-varying algorithm for the three-dimensional pure proportional navigation (PPN) guidance problem is presented using the differential geometric (DG) guidance command. To this end, classical differential geometry theory is introduced, firstly, to transform and modify the DG guidance curvature command so as to facilitate the practical implementation and to avoid singularity of the guidance command. Then, a new gain-varying guidance scheme is developed using the modified DG guidance command, as well as the principle of the PPN guidance law, the new guidance law does not need the evaluation of time-to-go information. Furthermore, the capture analysis of the PPN-type guidance law is qualitatively studied in terms of the DG formulations, and a post-launch capture condition is derived and expressed in geometric terms. Simulation results demonstrate that the proposed guidance algorithm performs better than the conventional PPN guidance law in the case of intercepting maneuvering targets.
During the past decade, digital integrated circuits, especially silicon ECL and Gallium Arsenide (GaAs) devices, have become much faster, supporting clock rates of 0.5-2 GHz, and generating off-chip signal rise times ...
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During the past decade, digital integrated circuits, especially silicon ECL and Gallium Arsenide (GaAs) devices, have become much faster, supporting clock rates of 0.5-2 GHz, and generating off-chip signal rise times as fast as 100 ps. These faster chips are placing considerable pressure on the electrical characteristics of both single chip packages and more recently multichip modules (MCM's), since the packages must be designed not to degrade the performance of the chips themselves. Further, not only must the package assure the integrity of the propagating wavefronts in the package interconnects;the effects of crosstalk, reflections, and other parasitics must all be taken into account simultaneously if the final package design is to be adequate. Because the complexity of the electronic packages under development for high clock rate digital signal processors increasingly overwhelmed the simulation tools which were available to us, we have developed a new, comprehensive electromagnetic (EM) modeling tool, the Networking algorithm, which is capable of simulating on a digital computer the complexities inherent in real-world interconnects and packages, including simultaneous treatment of the effects of mixed types of transmission line interconnects (i.e., mixtures of stripline, microstrip, and coplanar lines), stubs and branches, reflections, and crosstalk between multiple nets. In this paper we will describe the type of modeling tool which has been developed, discuss the mathematics of the Networking algorithm, and then present a number of actual examples taken from our high frequency digital package design work to show how such a computer-based EM modeling tool set can assist in the design of high performance packages.
The Bayesian Optimization algorithm (BOA) is one of the most prominent Estimation of Distribution algorithms. It can detect the correlation between multiple variables and extract knowledge on regular patterns in solut...
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The Bayesian Optimization algorithm (BOA) is one of the most prominent Estimation of Distribution algorithms. It can detect the correlation between multiple variables and extract knowledge on regular patterns in solutions. Bayesian Networks (BNs) are used in BOA to represent the probability distributions of the best individuals. The BN's construction is challenging since there is a trade-off between acuity and computational cost to generate it. This trade-off is determined by combining a search algorithm (SA) and a scoring metric (SM). The SA is responsible for generating a promising BN and the SM assesses the quality of such networks. Some studies have already analyzed how this relationship affects the learning process of a BN. However, such investigation had not yet been performed to determine the bond linking the selection of SA and SM and the BOA's output quality. Acting on this research gap, a detailed comparative analysis involving two constructive heuristics and four scoring metrics is presented in this work. The classic version of BOA was applied to discrete and continuous optimization problems using binary and floating-point representations. The scenarios were compared through graphical analyses, statistical metrics, and difference detection tests. The results showed that the selection of SA and SM affects the quality of the BOA results since scoring metrics that penalize complex BN models perform better than metrics that do not consider the complexity of the networks. This study contributes to a discussion on this metaheuristic's practical use, assisting users with implementation decisions.
The application of VHDL (VHSIC hardware description language) in the design and development of a custom DSP (digital signal processing) complex-to-magnitude circuit is described. The circuit produces the magnitude of ...
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The application of VHDL (VHSIC hardware description language) in the design and development of a custom DSP (digital signal processing) complex-to-magnitude circuit is described. The circuit produces the magnitude of a complex number using an approximation algorithm. The target implementation is a bit-serial architecture using a set of primitive operators for DSP design. The algorithm and architecture are investigated at the word level using the real-number type, and the results are applied to the bit level. It is found that VDHL provides strong support and clear documentation for each level of abstraction.
A method for applying combinatorial optimization algorithms to Energy Storage System (ESS) scheduling is presented in this paper. Scheduling is essential for the integration of ESS in electrical networks at grid level...
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A method for applying combinatorial optimization algorithms to Energy Storage System (ESS) scheduling is presented in this paper. Scheduling is essential for the integration of ESS in electrical networks at grid level or at consumer level to achieve the objectives of integration such as constraint management or energy cost reduction and for efficient storage dispatch. It also shows that for a time-of-use (ToU) tariff scheme based on the shape of the demand profile with higher prices tied to peak periods, effective load-leveling, and peak demand reduction always leads to energy cost reduction. While other methods usually require more information such as generation cost curves or ToU tariffs to schedule ESS, the proposed method uses only demand profile information and ESS parameters to achieve load-leveling and peak demand reduction and also considers the entire optimization time horizon. This is done by combining heuristic bin packing and subset sum algorithms with specific modifications to the standard forms and through transformations. A case study is presented in which the algorithm is used to schedule household ESS with repurposed electric vehicle batteries and the results are compared to a demand response scheme on the same setup.
It is well known that de offsets degrade the performance of analog adaptive filters. In this paper, the effects of de offsets on four variations of the stochastic gradient algorithm are analyzed. Assuming a Gaussian p...
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It is well known that de offsets degrade the performance of analog adaptive filters. In this paper, the effects of de offsets on four variations of the stochastic gradient algorithm are analyzed. Assuming a Gaussian probability distribution for the input signal and error signal, the output mean squared error (MSE) performance in the presence of de offsets is evaluated for each of the algorithms. The theoretical work is compared with computer simulations and the results, together with convergence properties of each of the algorithms and their respective hardware requirements, are used in selecting the most appropriate algorithm. Although a Gaussian input distribution is assumed, it may reasonably be inferred that the critical results obtained should also hold for other input distributions.
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