A qualitative theory for synchronous discrete time Hopfield-type neural networks is established. The authors' objectives are accomplished in two phases. First, they address the analysis of the class of neural netw...
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A qualitative theory for synchronous discrete time Hopfield-type neural networks is established. The authors' objectives are accomplished in two phases. First, they address the analysis of the class of neural networks considered. Next, making use of these results, they develop a synthesis procedure for the class of neural networks considered. In the analysis section, techniques from the theory of large-scale interconnected dynamical systems are used to derive tests for the asymptotic stability of an equilibrium of the neural network. Estimates for the rate at which the trajectories of the network will converge from an initial condition to a final state are presented. In the synthesis section the stability tests from the analysis section are used as constraints to develop a designalgorithm for associative memories. The algorithm presented guarantees that each desired memory will be stored as an equilibrium, and that each desired memory will be asymptotically stable. The applicability of these results is demonstrated by means of two specific examples.< >
In this paper, we study generalized Reed-Solomon codes (GRS codes) over commutative and noncommutative rings, we show that the classical Welch-Berlekamp and Guruswami-Sudan decoding algorithms still hold in this conte...
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In this paper, we study generalized Reed-Solomon codes (GRS codes) over commutative and noncommutative rings, we show that the classical Welch-Berlekamp and Guruswami-Sudan decoding algorithms still hold in this context, and we investigate their complexities. Under some hypothesis, the study of noncommutative GRS codes over finite rings leads to the fact that GRS codes over commutative rings have better parameters than their noncommutative counterparts. Also, GRS codes over finite fields have better parameters than their commutative rings counterparts. But we also show that given a unique decoding algorithm for a GRS code over a finite field, there exists a unique decoding algorithm for a GRS code over a truncated power series ring with a better asymptotic complexity. Moreover, we generalize a lifting decoding scheme to obtain new unique and list decoding algorithms designed to work when the base ring is, for example, a Galois ring or a truncated power series ring or the ring of square matrices over the latter ring.
Random multiple-access algorithms are used to control the accessing of a common communication channel by a large population of bursty channel users. For such algorithms, the induced transmission delay is a key perform...
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Random multiple-access algorithms are used to control the accessing of a common communication channel by a large population of bursty channel users. For such algorithms, the induced transmission delay is a key performance measure. A systematic method for finding the delay characteristics of random multiple-access algorithms, whose delay process is regenerative, is presented. The method uses a powerful result from the theory of regenerative processes, in effect, to reduce the problem of determining the delay moments to the problem of solving denumerable dimensional systems of linear equations. Techniques for finding tight bounds on the solutions of such systems are presented. The "0.487" algorithm is used to exemplify the method.
Techniques for gauging the accuracy of approximate testability measures that estimate the random-pattern testability of gate-level faults in designs with combinational logic are considered. The measures examined are o...
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Techniques for gauging the accuracy of approximate testability measures that estimate the random-pattern testability of gate-level faults in designs with combinational logic are considered. The measures examined are overall fault-exposure distribution, high coverage, and fault grading. Sampling techniques are compared with the Stafan and Protest approximate testability measures. For random-pattern testing, it is clear that state-of-the-art testability measures like Stafan and Protest do provide some information about the testability of single faults or complete designs, but this information is not accurate; in many areas of use they cannot compete with carefully chosen sampling techniques. The three techniques described here are applicable to testing strategies other than the random-pattern testing of stuck-at faults; they are equally useful in a weighted random-pattern testing environment, for example.
Part I derives a new topological formula for the terminalpair reliability of complex networks. The formula generates only non-cancelling terms. The non-cancelling terms in the reliability expression correspond one-to-...
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Part I derives a new topological formula for the terminalpair reliability of complex networks. The formula generates only non-cancelling terms. The non-cancelling terms in the reliability expression correspond one-to-one with the acyclic subgraphs of the given probabilistic graph. Part II introduces the concept of neutral sequences in acyclic graphs; several of their important properties are established. Based on these results a powerful algorithm for generating the reliability expression is presented. The reliability expression is obtained in symbolic factored form. Examples indicate that the present algorithm is appreciably faster than earlier methods. The properties of cyclic and acyclic graphs established in this paper are significant new results in the theory of digraphs and have further ramifications and wider application than in reliability.
There are many different techniques for designing and implementing algorithms for the control of periodic disturbances. The methods range between discrete and analog, time invariant and adaptive, and time domain and f...
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There are many different techniques for designing and implementing algorithms for the control of periodic disturbances. The methods range between discrete and analog, time invariant and adaptive, and time domain and frequency domain approaches. The goal of this paper is to provide an overview of the methods available for such narrow-band control and to show, through analysis, the strong similarities between the different methodologies. The analysis of linear time invariant feedback systems results in a suggestion of how to extend two of the LQ-based multiple-input multiple-output methodologies to achieve improved performance and stability robustness properties. In the analysis of the adaptive feedforward methods, it is concluded that the popular filtered-x LMS algorithm is useful for implementation, but is best analyzed from a classical linear time invariant feedback perspective. This perspective also then results in a suggestion of how to extend the multiple error LMS algorithm to achieve improved performance and stability robustness. Stability bounds of the adaptive feedforward approaches are derived in terms of allowable model error.
A procedure for the design of equiripple digital differentiators (DD's) and Hilbert transformers (HT's) using a weighted least-squares technique is described. This procedure involves an iterative algorithm in ...
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A procedure for the design of equiripple digital differentiators (DD's) and Hilbert transformers (HT's) using a weighted least-squares technique is described. This procedure involves an iterative algorithm in which the appropriate frequency-dependent weighting function that yields an equiripple design is determined. Our procedure is used in conjunction with prediction techniques for the DD and HT lengths to design DD's and HT's, respectively, satisfying prescribed specifications.
MPEG-4's many algorithms and high-performance requirements pose a challenge for designers of a new generation of flexible, low-power coder/decoder VLSI implementations for mobile and portable applications.
MPEG-4's many algorithms and high-performance requirements pose a challenge for designers of a new generation of flexible, low-power coder/decoder VLSI implementations for mobile and portable applications.
The use of the tensor product as a tool for modeling and developing digital signal processing algorithms is discussed. A precise mathematical definition of the tensor product is established along with several importan...
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The use of the tensor product as a tool for modeling and developing digital signal processing algorithms is discussed. A precise mathematical definition of the tensor product is established along with several important properties. Special tensor matrices suited for implementation on various computer architectures are then identified. The notion of the stride permutation matrix is introduced as a method of modeling operand addressing. An important connection between tensor matrices and stride permutations is made explicit. By identifying particular tensor matrices suited for implementation on a given machine the tensor product has been transformed from a mathematical convenience into an extremely useful tool for matching algorithms to computer architectures. Several design examples in which a tensor matrix multiplication is implemented on several radically different types of computer architectures are presented.< >
New algorithms used in the GOALIE2 circuit extraction system are presented that are based on representing VLSI layout geometries as trapezoids. These include polygon-to-trapezoid decomposition, scanline management, an...
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New algorithms used in the GOALIE2 circuit extraction system are presented that are based on representing VLSI layout geometries as trapezoids. These include polygon-to-trapezoid decomposition, scanline management, and output sorting. The scanline algorithm virtually eliminates the redundant computation present in similar systems. It solves the VLSI layout analysis problem in O(n+k) expected time and O( square root n) expected space, where n is the total number of input segments and k is the total number of intersection points. The new scanline algorithm is robust in what it will maintain its performance over a wide range of layout styles. Experimental results show that the running time is O(n/sup 1.0547/), i.e. that these algorithms enable one to perform VLSI layout analysis in nearly linear time.< >
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