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LIST VITERBI DECODING algorithmS WITH APPLICATIONS

IEEE TRANSACTIONS ON COMMUNICATIONS 1994年第2-4期42卷 313-323页

作者： SESHADRI, N SUNDBERG, CEW AT&T Bell Labs. Murray Hill NJ

A list Viterbi decoding algorithm (LVA) produces a rank ordered list of the L globally best candidates after a trellis search. Here, we present two such algorithms, (i) a parallel LVA that simultaneously produces the L best candidates and (ii) a serial LVA that iteratively produces the k(th) best candidate based on knowledge of the previously found k-1 best paths. The application of LVA to a concatenated communication system consisting of an inner convolutional code and an outer error detecting code is considered in detail. analysis as well as simulation results show that significant improvement in error performance is obtained when the inner decoder, which is conventionally based on the Viterbi algorithm (VA), is replaced by the LVA. An improvement of up to 3 dB is obtained for the additive white Gaussian noise (AWGN) channel due to an increase in the minimum Euclidean distance. Ever larger gains are obtained for the Rayleigh fading channel due to an increase in the time diversity. It is also shown that a 10% improvement in throughput is obtained along with significantly reduced probability of a decoding failure for a hybrid FEC/ARQ scheme with the inner code being a rate compatible punctured convolutional (RCPC) code.

关键词： Viterbi algorithm Iterative algorithms AWGN Iterative decoding Convolutional codes Concatenated codes Performance analysis algorithm design and analysis Analytical models Additive white noise

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A DATA-DRIVEN INTERMEDIATE LEVEL FEATURE-EXTRACTION algorithm

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IEEE TRANSACTIONS ON PATTERN analysis AND MACHINE INTELLIGENCE 1989年第7期11卷 749-758页

作者： CHEN, DS General Motors Tech. Center Warren MI USA

An algorithm is presented that is based on the regression updating theory for fitting linearly parameterizable curves without prior classification of edge data. An initial estimate of a hypothesized curve is first obtained by a statistical windowing technique. A search region is determined and iteratively grown. Edge points in the search region are tested for their goodness-of-fit to the previous estimate. The estimate is iteratively updated with the edge points that have favorable goodness-of-fit measures. The edge points having poor goodness-of-fit measures are rejected as outliers. The algorithm drives the estimate to converge to a final solution. By repeatedly applying this procedure to the edge data excluded from the previous fitting, all the underlying curves are reconstructed. The major feature that distinguishes this approach from that of others is that classifying the edge data prior to fitting is not required. Advantages of this algorithm are: (1) the fitting procedure achieves higher robustness and accuracy by dynamically analyzing the data consistency; (2) the computational complexity increases only linearly with the number of edge data; (3) the algorithm readily extends to reconstruct surfaces from range data. Thus the algorithm provides a powerful technique enabling a data-driven intermediate-level vision module to extract parametric features needed for higher-level processing.

关键词： Feature extraction Iterative algorithms Curve fitting Surface fitting Testing Robustness Data analysis algorithm design and analysis Computational complexity Surface reconstruction INSPEC: Controlled Indexing iterative methods computer vision curve fitting INSPEC: Non-Controlled Indexing edge points computer vision curve fitting iterative methods data-driven intermediate level feature extraction algorithm regression updating theory hypothesized curve statistical windowing technique goodness-of-fit

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RECURSIVE FORWARD DYNAMICS FOR MULTIPLE ROBOT ARMS MOVING A COMMON TASK OBJECT

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IEEE TRANSACTIONS ON ROBOTICS AND AUTOMATION 1989年第4期5卷 510-521页

作者： RODRIGUEZ, G Jet Propulsion Laboratory California Institute of Technology Pasadena CA USA

Recursive forward dynamics algorithms are developed and presented for an arbitrary number of robot arms moving a commonly held object. The multiarm forward dynamics solutions provide a thorough physical and mathematical understanding of the way several arms behave in response to a set of applied joint moments. The forward dynamics algorithms also provide the necessary analytical foundation for conducting analysis and simulation studies. The multiarm algorithms are based on the filtering and smoothing approach advanced by the author for single-arm dynamics (IEEE Trans. Robots Autom., Dec. 1987, no.6, Dec. 1987 pp.624-39), and they can be built up modularly from the single-arm algorithms. The algorithms compute recursively the joint angle-accelerations, the contact forces, and the task-object accelerations. algorithms are also developed to evaluate in closed form the linear transformations from the active joint moments to the joint angle accelerations, to the task object accelerations, and to the task-object contact forces. A possible computing architecture is presented as a precursor to a more complete investigation of the computational performance of the dynamics algorithms.< >

关键词： Robots Manipulators Heuristic algorithms Acceleration algorithm design and analysis Arm Computational modeling Analytical models Filtering algorithms Smoothing methods

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Faulty processor identification for a multiprocessor system under the Malek model using an improved binary bat algorithm

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JOURNAL OF SUPERCOMPUTING 2023年第4期79卷 3791-3820页

作者： Gui, Weixia Pan, Fulai Zhu, Dandan Li, Feng Guangxi Univ Finance & Econ Coll Informat & Stat Nanning 530003 Guangxi Peoples R China China Railway Nanning Bur Grp Co Ltd Informat Technol Inst Nanning 530029 Guangxi Peoples R China Guangxi Univ Sch Comp & Elect Informat Nanning 530004 Guangxi Peoples R China

A multiprocessor system should be able to identify and eliminate faults in time to avoid the paralysis of a whole system. This paper proposes an improved binary bat algorithm to identify faulty processors in a multiprocessor system. Compared with most existing works based on metaheuristic algorithms, the proposed algorithm employs a random initial population and does not require transfer functions. The exclusive-OR operation in the velocity equation is used to measure the distance between two individuals in binary space. To improve population diversity and avoid local optima, the mutation operator is integrated into the position update equation. A new local search strategy is proposed to strengthen the ability of local search in binary space. Experimental results show that the proposed algorithm based on the Malek model can maintain approximately 100% diagnostic accuracy in a small random initial population with fewer iterations and less CPU running time.

关键词： algorithm design and analysis Boolean algebra Computational intelligence Metaheuristic algorithms Multiprocessor systems Optimization methods System-level fault diagnosis

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SECURITY AND PERFORMANCE OPTIMIZATION OF A NEW DES DATA ENCRYPTION CHIP

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1988年第3期23卷 647-656页

作者： VERBAUWHEDE, I HOORNAERT, F VANDEWALLE, J DEMAN, HJ CATHOLIC UNIV LEUVEN ESAT LABB-3030 HEVERLEBELGIUM

The implementation of a high-performance data encryption standard (DES) data encryption chip is presented. At the system design level, cryptographical optimizations and equivalence transformations lead to a very efficient floorplan with minimal routing, which otherwise would present a serious problem for data-scrambling algorithms. These optimizations, which do not compromise the DES algorithm nor the security, are combined with a highly structured design and layout strategy. Novel CAD tools are used at different steps in the design process. The result is a single chip of 25 mm/sup 2/ in 3- mu m double-metal CMOS. Functionality tests show that a clock of 16.7 MHz can be applied, which means that a 32-Mb/s data rate can be achieved for all eight byte modes. This is the fastest DES chip reported yet, allowing equally fast execution of all four DES modes of operation, due to an original pipeline architecture.< >

关键词： Data security Cryptography design optimization Routing algorithm design and analysis design automation Process design Testing Clocks Pipelines

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NEURAL NETWORK ARCHITECTURES FOR ROBOTIC APPLICATIONS

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IEEE TRANSACTIONS ON ROBOTICS AND AUTOMATION 1989年第5期5卷 641-657页

作者： KUNG, SY HWANG, JN Dept. of Electr. Eng. Princeton Univ. NJ USA Department of Electrical Engineering Princeton University Princeton NJ USA Department of Electrical Engineering University of Washington Seattle WA USA

The authors propose a ring VLSI systolic architecture for implementing artificial neural networks (ANNs) with applications to robotic processing. Key design issues concerning algorithms, applications, and architectures are examined. A variety of neural networks is considered, including single-layer feedback neural networks, competitive learning networks, and multilayer feed-forward networks. It is demonstrated that the ANNs are suitable to all three levels of robotic processing applications including task planning, path planning, and path control levels. For these applications, a programmable systolic array is developed than can exploit the strength of VLSI to provide intensive and pipelined computing. Both the retrieving and learning phases are integrated in the design. The proposed architecture, which is more versatile than other existing ANNs, can accommodate all the useful neural networks for robotic processing.< >

关键词： Neural networks Robots Artificial neural networks Multi-layer neural network Very large scale integration Feedforward neural networks Path planning Process design algorithm design and analysis Neurofeedback

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FPGA-based Controllers

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IEEE INDUSTRIAL ELECTRONICS MAGAZINE 2011年第1期5卷 14-26页

作者： Monmasson, Eric Idkhajine, Lahoucine Naouar, Mohamed Wissem Currently a full professor and head of the Institut Universitaire Professionnalis&#x00E9 de G&#x00E9 nie Electrique et d&#x0027 Informatique Indutrielle (IUP GEII) University of Cergy-Pontoise in France.

This article presents the benefits of using field-programmable gate array (FPGA)-based controllers for power electronics and drive applications. For this purpose, an algorithm perspective is first proposed, where it is stated that, depending on the intrinsic parallelism properties as well as level of complexity, it makes sense to implement each control algorithm on a specific hardware and/or software architecture to get the best performances in terms of execution time or the best ratio performance versus cost. Then, an application perspective is proposed where the constraints specifically linked to the control of power converters are discussed.

关键词： Field programmable gate arrays algorithm design and analysis Digital signal processing Hardware Hardware design languages Software algorithms Computer architecture

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A CLASS OF SYSTOLIZABLE IIR DIGITAL-FILTERS AND ITS design FOR PROPER SCALING AND MINIMUM OUTPUT ROUNDOFF NOISE

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS 1990年第10期37卷 1217-1230页

作者： LEI, SM YAO, K UNIV CALIF LOS ANGELES SCH ENGN & APPL SCIDEPT ELECT ENGNLOS ANGELESCA 90024

A class of infinite impulse response (IIR) digital filters with a systolizable structure is proposed and its synthesis is investigated. The systolizable structure consists of pipelineable regular modules with local connections and is suitable for VLSI implementation. It is capable of achieving high performance as well as high throughput. This class of filter structure provides certain degrees of freedom that can be used to obtain some desirable properties for the filter. Techniques of evaluating the internal signal powers and the output roundoff noise of the proposed filter structure are developed. Based upon these techniques, a well-scaled IIR digital filter with minimum output roundoff noise is designed with a local optimization approach. The internal signals of all the modes of this filter are scaled to unity in the l/sup 2/-norm sense. Compared to the Rao-Kailath (1984) orthogonal digital filter and the Gray-Markel (1973) normalized-lattice digital filter, this filter has better scaling properties and lower output roundoff noise.>

关键词： Digital filters Very large scale integration Signal processing algorithms IIR filters algorithm design and analysis Signal design Digital signal processing Lattices Transfer functions Signal synthesis

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HIGH-QUALITY AUDIO TRANSFORM CODING AT 64-KBPS

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IEEE TRANSACTIONS ON COMMUNICATIONS 1994年第11期42卷 3010-3019页

作者： MAHIEUX, Y PETIT, JP Centre National d''Etudes Des Telecommunications Lannion France

This paper presents a transform coding algorithm devoted to high quality audio coding at a bit rate of 64 kbps per monophonic channel. It enables the transmission of a high quality stereo sound through the basic access (2B channels) of ISDN. Although a complete system including framing, synchronization and error correction has been developed, only the bit rate compression algorithm is described here. A detailed analysis of the signal processing techniques such as the time/frequency transformation, the pre-echo reduction by adaptive filtering, the fast algorithm computations, etc., is provided. The use of psychoacoustical properties is also precisely reported. Finally, some subjective evaluation results and one real time implementation of the coder using the ATT DSP32C digital signal processor are presented.

关键词： Transform coding Signal processing algorithms Bit rate Audio coding ISDN Frequency synchronization Error correction Compression algorithms Signal analysis algorithm design and analysis

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SERVICE RESTORATION IN DISTRIBUTION NETWORKS VIA NETWORK RECONFIGURATION

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IEEE TRANSACTIONS ON POWER DELIVERY 1992年第2期7卷 952-958页

作者： SHIRMOHAMMADI, D PACIFIC GAS & ELECT CO SAN FRANCISCOCA 94106

This paper describes the principle and the implementation of a heuristic methodology to restore service to the isolated portions of a distribution system via network reconfiguration. The methodology determines a minimum possible number of switching operations needed to restore service to network branches that are isolated due to forced or scheduled outages. Major operating constraints are taken into account in the restoration. A computer program has been developed based on this methodology for use in operations planning of the PG&E distribution system.

关键词： Intelligent networks Switches Processor scheduling Distributed computing Substations Senior members Automation Power & Energy Society Robustness algorithm design and analysis

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