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THE STUDY OF LOGARITHMIC IMAGE-PROCESSING MODEL AND ITS APPLICATION TO IMAGE-ENHANCEMENT

IEEE TRANSACTIONS ON IMAGE PROCESSING 1995年第4期4卷 506-512页

作者： DENG, G CAHILL, LW TOBIN, GR Dept. of Electron. Eng. La Trobe Univ. Bundoora Vic.

This correspondence describes a new implementation of Lee's image enhancement algorithm [8], This approach, based on the logarithmic image processing (LIP) model, can simultaneously enhance the overall contrast and the sharpness of an image, A normalized complement transform has been proposed to simplify the analysis and the implementation of the LIP model-based algorithms, This new implementation has been compared with histogram equalization and Lee's original algorithm.

关键词： Image processing Image enhancement Histograms Humans Visual system algorithm design and analysis Dynamic range Pixel Brightness Artificial intelligence

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A LOOSE-PATTERN PROCESS APPROACH TO CLUSTERING FUZZY DATA SETS

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IEEE TRANSACTIONS ON PATTERN analysis AND MACHINE INTELLIGENCE 1985年第3期7卷 366-372页

作者： GU, T DUBUISSON, B University of Technology of Compiegne 6020 Compiegne Cedex France

A loose-pattern process approach to clustering sets consists of three main computations: loose-pattern reject option, tight-pattern classifcation, and loose-pattern assigning classes. The loose-pattern rejection is implemented using a rule based on q nearest neighbors of each point. Two clustering methods, GLC and OUPIC, are introduced as tight-pattern clustering techniques. The decisions of loose-pattern assigning classes are related to a heuristic membership function. The function and experiments with one set is discussed.","doi":"10.1109/TPAMI.1985.4767669","publicationTitle":"IEEE Transactions on Pattern analysis and Machine Intelligence","startPage":"366","endPage":"372","rightsLink":"http://***/AppDispatchServlet?publisherName=ieee&publication=0162-8828&title=A+Loose-Pattern+Process+Approach+to+Clustering+Fuzzy+Data+Sets&isbn=&publicationDate=May+1985&author=Tao+Gu&ContentID=10.1109/TPAMI.1985.4767669&orderBeanReset=true&startPage=366&endPage=372&volumeNum=PAMI-7&issueNum=3","displayPublicationTitle":"IEEE Transactions on Pattern analysis and Machine Intelligence","pdfPath":"/iel5/34/4767650/***","keywords":[{"type":"IEEE Keywords","kwd":["Fuzzy sets","Kernel","Random variables","algorithm design and analysis","Convergence","Fast Fourier transforms","Sorting","Clustering algorithms","Probability","Statistics"]},{"type":"Author Keywords ","kwd":["membership function","Classification","clustering algorithm","fuzzy discrimination","fuzzy set"]}],"allowComments":false,"pubLink":"/xpl/***?punumber=34","issueLink":"/xpl/***?isnumber=4767650","standardTitle":"A Loose-Pattern Process Approach to Clustering Fuzzy Data Sets

关键词： Fuzzy sets Kernel Random variables algorithm design and analysis Convergence Fast Fourier transforms Sorting Clustering algorithms Probability Statistics Author Keywords membership function Classification clustering algorithm fuzzy discrimination fuzzy set

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ARCHITECTURAL LEVEL TEST-GENERATION FOR MICROPROCESSORS

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IEEE TRANSACTIONS ON COMPUTER-AIDED design OF INTEGRATED CIRCUITS AND SYSTEMS 1994年第10期13卷 1288-1300页

作者： LEE, JS PATEL, JH UNIV ILLINOIS CTR RELIABLE & HIGH PERFORMANCE COMPURBANAIL 61801

Hierarchically designed microprocessor-like VLSI circuits have complex data paths and embedded control machines to execute instructions. When a test pattern has to be applied to the input of an embedded module, determination of a sequence of instructions, which will apply this pattern and propagate the fault effects, is extremely difficult. After the instruction sequence is derived, to assign values at all interior lines without conflicts is also very difficult. In this paper, we propose a separation of test generation process into two phases: path analysis and value analysis. In the phase of path analysis, a new methodology for automatic assembly of a sequence of instructions is proposed to satisfy the internal test goals. In the phase of value analysis, an equation-solving algorithm is used to compute an exact value solution for all interior lines. This new ATPG methodology containing techniques for both path and value analysis forms a complete solution for a variety of microprocessor-like circuits. This new approach has been implemented and experimented on six high-level circuits. The results show that our approach is very effective in achieving complete automation for high-level test generation.

关键词： Microprocessors Circuit testing Automatic testing Very large scale integration Circuit faults Assembly algorithm design and analysis Equations Automatic test pattern generation Automation

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Soft synchronization of direct sequence spread-spectrum signals

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IEEE TRANSACTIONS ON COMMUNICATIONS 1996年第11期44卷 1527-1536页

作者： Agee, BG Kleinman, RJ Reed, JH APPL SIGNAL TECHNOL INC SUNNYVALECA 94086 VIRGINIA TECH BRADLEY DEPT ELECT ENGNMOBILE & PORTABLE RADIO RES GRPBLACKSBURGVA 24061

A new technique for soft synchronization of direct-sequence spread-spectrum (DSSS) signals is presented. The technique, referred to here as the dominant mode despreading (DMDS) algorithm, exploits the eigenstructure of a frequency-channelized DSSS signal to estimate the spreading code and underlying message sequence of the signal. Unlike other despreading techniques, the estimate of the code and data improves steadily with the number of code repeats. The technique is applicable to arbitrary spreading codes and message sequences and can operate in environments containing arbitrary levels of white background noise, and for signals with arbitrary unknown timing phase or carrier frequency offset. The technique requires the DSSS signal to have a constant-modulus spreading code and unrelated message and code-repeat rates. This paper introduces the basic technique, theoretically analyzes the algorithm to prove convergence under infinite time-average conditions, and demonstrates the algorithm via computer simulation for a single DSSS signal received in the presence of white Gaussian noise.

关键词： Spread spectrum communication Frequency synchronization Frequency estimation Background noise Timing Signal analysis algorithm design and analysis Convergence Computer simulation Gaussian noise

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RECURSIVE FAST algorithmS AND THE ROLE OF THE TENSOR PRODUCT

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 1992年第12期40卷 2921-2930页

作者： GRANATA, J CONNER, M TOLIMIERI, R Center for Large Scale Computation City University of New York New York NY USA

The tensor product has proven to been a powerful linguistic tool for modeling and designing FFT algorithms. The benefit of the tensor product approach lies in the strong connection between certain tensor product constructs and important computer architectures. In this paper the scope of the tensor product approach is generalized to include a much larger class of fast recursive algorithms. This greatly enhances the versatility of the tensor product technique and also brings many different algorithms to the level of understanding and flexibility enjoyed by the FFT.

关键词： Tensile stress Signal processing algorithms Computer architecture Flow graphs Matrix decomposition algorithm design and analysis Signal design Matrices History

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Parallel Graph Partitioning for Complex Networks

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2017年第9期28卷 2625-2638页

作者： Meyerhenke, Henning Sanders, Peter Schulz, Christian Karlsruhe Inst Technol D-76131 Karlsruhe Germany Univ Vienna A-1010 Vienna Austria

Processing large complex networks like social networks or web graphs has attracted considerable interest. To do this in parallel, we need to partition them into pieces of roughly equal size. Unfortunately, previous parallel graph partitioners originally developed for more regular mesh-like networks do not work well for complex networks. Here we address this problem by parallelizing and adapting the label propagation technique originally developed for graph clustering. By introducing size constraints, label propagation becomes applicable for both the coarsening and the refinement phase of multilevel graph partitioning. This way we exploit the hierarchical cluster structure present in many complex networks. We obtain very high quality by applying a highly parallel evolutionary algorithm to the coarsest graph. The resulting system is both more scalable and achieves higher quality than state-of-theart systems like ParMetis or PT-Scotch. For large complex networks the performance differences are very big. As an example, our algorithm partitions a web graph with 3.3 G edges in 16 seconds using 512 cores of a high-performance cluster while producing a high quality partition-none of the competing systems can handle this graph on our system.

关键词： Load balancing and task assignment graph algorithms combinatorial algorithms algorithm design and analysis

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Efficient algorithms for parallelizing Monte Carlo simulations for 2D Ising spin models

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JOURNAL OF SUPERCOMPUTING 2008年第3期44卷 274-290页

作者： Santos, Eunice E. Rickman, Jeffrey M. Muthukrishnan, Gayathri Feng, Shuangtong Virginia Polytech Inst & State Univ Dept Comp Sci Blacksburg VA 24061 USA Lehigh Univ Dept Mat Sci & Engn Bethlehem PA 18015 USA

In this paper, we design and implement a variety of parallel algorithms for both sweep spin selection and random spin selection. We analyze our parallel algorithms on LogP, a portable and general parallel machine model. We then obtain rigorous theoretical runtime results on LogP for all the parallel algorithms. Moreover, a guiding equation is derived for choosing data layouts (blocked vs. stripped) for sweep spin selection. In regard to random spin selection, we are able to develop parallel algorithms with efficient communication schemes. We introduce two novel schemes, namely the FML scheme and the alpha-scheme. We analyze randomness of our schemes using statistical methods and provide comparisons between the different schemes.

关键词： Ising model LogP model parallel computing algorithm design and analysis computational science performance prediction parallel models data layout optimization

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Resolution limits in signal recovery

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 1996年第3期44卷 546-561页

作者： Dharanipragada, S Arun, KS UNIV ILLINOIS DEPT ELECT & COMP ENGN COORDINATED SCI LAB URBANA IL 61801 USA

Resolution analysis for the problem of signal recovery from finitely many linear measurements is the subject of this paper, The classical Rayleigh limit serves only as a lower bound on resolution since it does not assume any recovery strategy and is based only on observed data. We show that details finer than the Rayleigh limit can be recovered by simple linear processing that incorporates prior information, We first define a measure of resolution based on allowable levels of error that is more appropriate for current signal recovery strategies than the Rayleigh definition, In the practical situation in which only finitely many noisy observations are available, we have to restrict the class of signals in order to make the resolution measure meaningful, We consider the set of bandlimited and essentially timelimited signals since it describes most signals encountered in practice. For this set, we show how to precompute resolution limits from knowledge of measurement functionals, signal-to-noise ratio, passband, energy concentration regions, energy concentration factor, and a prescribed level of error tolerance, In the process, we also derive an algorithm for high-resolution signal recovery, We illustrate the results with examples in one and two dimensions.

关键词： Signal resolution Energy resolution Space vector pulse width modulation algorithm design and analysis Signal analysis Iterative algorithms Mammography Sampling methods X-ray imaging Performance analysis

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Estimation of parameters of exponentially damped sinusoids using fast maximum likelihood estimation with application to NMR spectroscopy data

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 1996年第9期44卷 2245-2259页

作者： Umesh, S Tufts, DW CUNY HUNTER COLL DEPT PHYS & ASTRONNEW YORKNY 10021 UNIV RHODE ISL DEPT ELECT ENGNKINGSTONRI 02881

In this paper, we present fast maximum likelihood (FML) estimation of parameters of multiple exponentially damped sinusoids, The FML algorithm was motivated by the desire to analyze data that have many closely spaced components, such as the NMR spectroscopy data of human blood plasma, The computational efficiency of FML lies in reducing the multidimensional search involved in ML estimation into multiple 1-D searches, This is achieved by using our knowledge of the shape of the compressed likelihood function (CLF) in the parameter space. The proposed FML algorithm is an iterative method that decomposes the original data into its constituent signal components and estimates the parameters of the individual components efficiently using our knowledge of the shape of the CLF, The other striking features of the proposed algorithm are that it provides procedures for initialization, has a fast converging iteration stage, and makes use of the information extracted in preliminary iterations to segment the data suitably to increase the effective signal-to-noise ratio (SNR). The computational complexity and the performance of the proposed algorithm are compared with other existing methods such as those based on linear prediction, KiSS/IQML, alternating projections (AP), and (EM).

关键词： Parameter estimation Maximum likelihood estimation Shape Iterative algorithms Data analysis algorithm design and analysis Nuclear magnetic resonance Spectroscopy Humans Blood

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IS REDUNDANCY NECESSARY TO REDUCE DELAY

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IEEE TRANSACTIONS ON COMPUTER-AIDED design OF INTEGRATED CIRCUITS AND SYSTEMS 1991年第4期10卷 427-435页

作者： KEUTZER, K MALIK, S SALDANHA, A AT&T BELL LABS COMP SYST RES LABMURRAY HILLNJ 07974 UNIV CALIF BERKELEY DEPT ELECT ENGN & COMP SCIBERKELEYCA 94720

Logic optimization procedures principally attempt to optimize three criteria: performance, area, and testability. The relationship between area optimization and testability has recently been explored. As to the relationship between performance and testability, experience has shown that performance optimizations can, and do in practice, introduce single stuck-at-fault redundancies into designs. Are these redundancies necessary to increase performance or are they only an unnecessary by-product of performance optimization? In this paper we give a constructive resolution of this question in the form of an algorithm that takes as input a combinational circuit and returns an irredundant circuit that is as fast. We demonstrate the utility of this algorithm on a well-known circuit, the carry-skip adder, and present a novel irredundant design of that adder. As our algorithm may either increase or decrease circuit area, we leave unresolved the question as to whether every circuit has an irredundant circuit that is at least as fast and is of equal or lesser area.

关键词： Delay Logic testing Circuit testing Optimization Adders Helium Minimization Marine vehicles Combinational circuits algorithm design and analysis

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