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Optimal control of discrete-time nonlinear heterogeneous multi-agent systems via a distributed DISOPE algorithm

OPTIMAL CONTROL APPLICATIONS & METHODS 2023年第1期44卷 148-169页

作者： Wang, Zhenhua Li, Junmin Xidian Univ Sch Math & Stat Xian Shaanxi Peoples R China Xianyang Normal Univ Sch Math & Stat Xianyang Shaanxi Peoples R China

A distributed offline DISOPE algorithm for optimal state synchronization of leader-follower systems with nonlinear discrete-time dynamics is considered, which integrates the model optimization idea and parameter estimation technique together. It can be seen that the convergent solutions of modified linear optimal control problems satisfy the optimality conditions of the original nonlinear optimization problem with non-LQ performance indices. The heterogeneous agents can cooperate and exchange information via network communication. Based on DISOPE algorithm, a distributed optimal control policy is obtained to assure state synchronization and minimize performance indices in finite time horizon. Finally, a simulation example is provided to illustrate the effectiveness of the distributed DISOPE algorithm.

关键词： algorithm mapping distributed DISOPE algorithm nonlinear discrete-time dynamics optimal state synchronization

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algorithm Implementation of On-Board SAR Imaging on FPGA+DSP Platform

Algorithm Implementation of On-Board SAR Imaging on FPGA+DSP...

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Signal, Information and Data Processing (ICSIDP), IEEE International Conference on

作者： Wenyue Yu Yizhuang Xie Dan Lu Bingyi Li He Chen Liang Chen Beijing Key Laboratory of Embedded Real-time Information Processing Technology Beijing Institute of Technology Beijing China Shanghai Institute of Satellite Engineering Shanghai China Beijing Institute of Technology Chongqing Innovation Center Chongqing China

ISBN: (数字)9781728123455

ISBN: (纸本)9781728123462

This paper introduces an effective parallel processing method to design the on-board SAR (Synthetic Aperture Radar) real time imaging processor using FPGA+DSP based on the high-resolution imaging algorithm. The architecture of this processor is designed based on the analysis of the algorithm operation characteristics and the inherent time relationship. In order to reduce the time consumption, pipeline and parallel joint processing method is applied. In addition, the system uses a combination of floating-point operations and fixed-point operations, which not only meets the imaging accuracy requirements but also saves the hardware scale of the system. The system requires 24s to focus the GF-3 stripmap SAR raw data with a granularity of 16384*16384 when works in 100MHz. The results demonstrate that our method was effective and the imaging quality can meet the requirements.

关键词： real-time sar imaging parallel processing architecture algorithm mapping

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A Flexible Data Scheduling Scheme for Block Cipher Processor

A Flexible Data Scheduling Scheme for Block Cipher Processor

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7th International Congress of Information and Communication Technology (ICICT)

作者： Li, Gongli Xu, Jinhui Dai, Zibin Wang, Shoucheng Zhu, Yufei Inst Informat Sci & Technol Zhengzhou 450001 Henan Peoples R China Henan Normal Univ Coll Comp & Informat Engn Xinxiang 453002 Peoples R China

In order to improve the performance of block cipher, clustered processor structure is put forward. How to schedule data in multiple clusters will influence the processor performance directly. Based on the analyzing characteristics of block cipher data flow, we propose a data scheduling scheme according to block width and operation mode. The final algorithm mapping and experiment results show that the data scheduling scheme not only meets the data distribution demand of different algorithms, but also reduces the number of instructions that the algorithms need, thus it can enhance the throughput of most algorithms.

关键词： block cipher data scheduling mode of operation algorithm mapping

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A Flexible Data Scheduling Scheme for Block Cipher Processor

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Procedia Computer Science 2017年 107卷 395-400页

作者： Gongli Li Jinhui Xu Zibin Dai Shoucheng Wang Yufei Zhu Institute of Information Science and Technology Zhengzhou 450001 China College of Computer & Information Engineering Henan Normal University Xinxiang 453002 China

关键词： block cipher data scheduling mode of operation algorithm mapping

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An Implementation of Multiple-Standard Video Decoder on a Mixed-Grained Reconfigurable Computing Platform

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2016年第5期E99D卷 1285-1295页

作者： Liu, Leibo Wang, Dong Chen, Yingjie Zhu, Min Yin, Shouyi Wei, Shaojun Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China Beijing Jiaotong Univ Inst Informat Sci Beijing Peoples R China

This paper presents the design of a multiple-standard 1080 high definition (HD) video decoder on a mixed-grained reconfigurable computing platform integrating coarse-grained reconfigurable processing units (RPUs) and FPGAs. The proposed RPU, including 16 x 16 multi-functional processing elements (PEs), is used to accelerate compute-intensive tasks in the video decoding. A soft-core-based microprocessor array is implemented on the FPGA and adopted to speed-up the dynamic reconfiguration of the RPU. Furthermore, a mail-box-based communication scheme is utilized to improve the communication efficiency between RPUs and FPGAs. By exploiting dynamic reconfiguration of the RPUs and static reconfiguration of the FPGAs, the proposed platform achieves scalable performances and cost trade-offs to support a variety of video coding standards, including MPEG-2, AVS, H.264, and HEVC. The measured results show that the proposed platform can support H.264 1080 HD video streams at up to 57 frames per second (fps) and HEVC 1080 HD video streams at up to 52fps under 250MHz, at the same time, it achieves a 3.6x performance gain over an industrial coarse-grained reconfigurable processor for H. 264 decoding, and a 6.43x performance boosts over a general purpose processor based implementation for HEVC decoding.

关键词： algorithm mapping coarse-grained reconfigurable array field-programmable gate array reconfigurable computing video decoding

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Design and Implementation of high speed and real-time SAR signal processing module based on TMS320C6678

Design and Implementation of high speed and real-time SAR si...

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International Conference on Mechatronics Engineering and Computing Technology (ICMECT)

作者： Feng, Yang Hu, Shanqing Li, Qing Long, Teng Beijing Inst Technol Radar Res Lab Beijing 100081 Peoples R China

ISBN: (纸本)9783038351153

In order to meet the requirements of high speed and real-time in SAR processing system, as well as breaking the bondage that traditional processing board is subject to the algorithm. This paper designs a generic mass storage real-time signal processing module with TI's latest multi-core DSP-TMS320C6678 based on OpenVPX high-speed serial bus standard. This module has standardized, modularized, reconfigurable characteristics. This paper discusses the design of this module and the implementation of typical parallel SAR imaging algorithm mapping on this module. This peocessing module has been applied in a variety of airborne SAR radar signal processing systems and fully validated its powerful processing ability and versatility.

关键词： SAR TMS320C6678 SRIO large-capacity cache algorithm mapping

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Event-driven Dynamic Platform Selection for Power-aware Real-time Anomaly Detection in Video

Event-driven Dynamic Platform Selection for Power-aware Real...

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9th International Conference on Computer Vision Theory and Applications (VISAPP)

作者： Blair, Calum G. Robertson, Neil M. Univ Edinburgh Inst Digital Commun Edinburgh Midlothian Scotland Heriot Watt Univ Visionlab Edinburgh Midlothian Scotland

ISBN: (纸本)9789897581335

In surveillance and scene awareness applications using power-constrained or battery-powered equipment, performance characteristics of processing hardware must be considered. We describe a novel framework for moving processing platform selection from a single design-time choice to a continuous run-time one, greatly increasing flexibility and responsiveness. Using Histogram of Oriented Gradients (HOG) object detectors and Mixture of Gaussians (MoG) motion detectors running on 3 platforms (FPGA, GPU, CPU), we characterise processing time, power consumption and accuracy of each task. Using a dynamic anomaly measure based on contextual object behaviour, we reallocate these tasks between processors to provide faster, more accurate detections when an increased anomaly level is seen, and reduced power consumption in routine or static scenes. We compare power-and speed-optimised processing arrangements with automatic event-driven platform selection, showing the power and accuracy tradeoffs between each. Real-time performance is evaluated on a parked vehicle detection scenario using the i-LIDS dataset. Automatic selection is 10% more accurate than power-optimised selection, at the cost of 12W higher average power consumption in a desktop system.

关键词： FPGA GPU Anomaly Detection Object Detection algorithm mapping

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Event-driven Dynamic Platform Selection for Power-aware Real-time Anomaly Detection in Video

Event-driven Dynamic Platform Selection for Power-aware Real...

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International Conference on Computer Vision Theory and Applications

作者： Calum G. Blair Neil M. Robertson Institute for Digital Communications University of Edinburgh Edinburgh U.K. Visionlab Heriot-Watt University Edinburgh U.K.

ISBN: (纸本)9781479976867

In surveillance and scene awareness applications using power-constrained or battery-powered equipment, performance characteristics of processing hardware must be considered. We describe a novel framework for moving processing platform selection from a single design-time choice to a continuous run-time one, greatly increasing flexibility and responsiveness. Using Histogram of Oriented Gradients (HOG) object detectors and Mixture of Gaussians (MoG) motion detectors running on 3 platforms (FPGA, GPU, CPU), we characterise processing time, power consumption and accuracy of each task. Using a dynamic anomaly measure based on contextual object behaviour, we reallocate these tasks between processors to provide faster, more accurate detections when an increased anomaly level is seen, and reduced power consumption in routine or static scenes. We compare power- and speed- optimised processing arrangements with automatic event-driven platform selection, showing the power and accuracy tradeoffs between each. Real-time performance is evaluated on a parked vehicle detection scenario using the i-LIDS dataset. Automatic selection is 10% more accurate than power-optimised selection, at the cost of 12W higher average power consumption in a desktop system.

关键词： FPGA GPU Anomaly Detection Object Detection algorithm mapping

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An Implementation of Configurable SIMD Core on FPGA

An Implementation of Configurable SIMD Core on FPGA

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2nd International Conference on Measurement, Instrumentation and Automation (ICMIA 2013)

作者： Wang, Guang Gao, Yinsheng Xian Univ Arts & Sci Xian 710065 Peoples R China

ISBN: (纸本)9783037857519

In order to meet the computing speed required by 4G wireless communications, and to provide the different data processing widths required by different algorithms, an SIMD (Single Instruction Multiple Data) core has been designed. The ISA (Instruction Set Architecture) and main components of the SIMD core are discussed focus on how the SIMD core can be configured. Finally, the simulation result of the multiplication of two 8*8 matrices is presented to show the execution of instructions in the proposed SIMD core, and the result verifies the correctness of the SIMD core design.

关键词： Architecture Configurable algorithm mapping SIMD core

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Reconfigurable baseband processing architecture for communication

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IET COMPUTERS AND DIGITAL TECHNIQUES 2011年第1期5卷 63-72页

作者： Lu, W. Q. Zhao, S. Zhou, X. F. Ren, J. Y. Sobelman, G. E. Fudan Univ State Key Lab ASIC & Syst Shanghai 201203 Peoples R China Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

The development of multiple communication standards and services has created the need for a flexible and efficient computational platform for baseband signal processing. Using a set of heterogeneous reconfigurable execution units (RCEUS) and a homogeneous control mechanism, the proposed reconfigurable architecture achieves a large computational capability while still providing a high degree of flexibility. Software tools and a library of commonly used algorithms are also proposed in this paper to provide a convenient framework for hardware generation and algorithm mapping. In this way, the architecture can be specified in a high-level language and it also provides increased hardware resource usage. Finally, we evaluate the system's performance on representative algorithms, specifically a 32-tap finite impulse response (FIR) filter and a 256-point fast Fourier transform (FFT), and compare them with commercial digital signal processor (DSP) chips as well as with other reconfigurable and multi-core architectures.

关键词： hardware resource usage digital signal processor chips Performance evaluation and testing high-level language fast Fourier transform reconfigurable architectures Digital signal processing hardware generation finite impulse response filter Integral transforms system performance evaluation Digital signal processing chips Microprocessors and microcomputers baseband signal processing FIR filters software tools performance evaluation homogeneous control mechanism reconfigurable baseband processing architecture digital signal processing chips communication standards multicore architectures Filtering methods in signal processing Computer architecture algorithm mapping heterogeneous reconfigurable execution units fast Fourier transforms

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