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10th International Conference on the Experience of Designing and Application of CAD Systems in Microelectronics

作者： Sergiyenko, Anatolij Maslennikow, Oleg Vinogradow, Yurij Koszalin University of Technology Poland National Technical University of Ukraine Ukraine

ISBN: (纸本)9789531841306

A method for mapping an algorithm, which is represented by the loop nest into the application specific structure is proposed. The method consists in translating the loop nest into the tensor equation. The tensor equation a set of structural solutions. The optimized solution finding consists in solving this equation in integers. The proposed limitations to the parts of the tensors help to derive. the pipelined structure and simplify the. mapping process. The method is illustrated by the example of the IIR-filter structure synthesis. It is intended for mapping DSP algorithms into FPGA.

关键词： algorithm mapping SDF DSP FPGA

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A Flexible Data Scheduling Scheme for Block Cipher Processor

A Flexible Data Scheduling Scheme for Block Cipher Processor

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7th International Congress of Information and Communication Technology (ICICT)

作者： Li, Gongli Xu, Jinhui Dai, Zibin Wang, Shoucheng Zhu, Yufei Inst Informat Sci & Technol Zhengzhou 450001 Henan Peoples R China Henan Normal Univ Coll Comp & Informat Engn Xinxiang 453002 Peoples R China

In order to improve the performance of block cipher, clustered processor structure is put forward. How to schedule data in multiple clusters will influence the processor performance directly. Based on the analyzing characteristics of block cipher data flow, we propose a data scheduling scheme according to block width and operation mode. The final algorithm mapping and experiment results show that the data scheduling scheme not only meets the data distribution demand of different algorithms, but also reduces the number of instructions that the algorithms need, thus it can enhance the throughput of most algorithms.

关键词： block cipher data scheduling mode of operation algorithm mapping

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AN ALGEBRAIC-THEORY FOR MODELING DIRECT INTERCONNECTION NETWORKS

AN ALGEBRAIC-THEORY FOR MODELING DIRECT INTERCONNECTION NETW...

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SUPERCOMPUTING 92 CONF

作者： KAUSHIK, SD SHARMA, S HUANG, CH JOHNSON, JR JOHNSON, RW SADAYAPPAN, P Department of Computer and Information Science Ohio State University Columbus 43210 OH United States Department of Mathematics and Computer Science Drexel University Philadelphia 19176 PA United States Department of Computer Science St. Cloud State University St. Cloud 56301 MN United States

ISBN: (纸本)0818626305

We present an algebraic theory based on tensor products for modeling direct interconnection networks. This algebraic theory has been used for designing and implementing block recursive numerical algorithms on shared-memory vector multiprocessors. This theory can be used for mapping algorithms expressed in tensor product form onto distributed-memory architectures. In this paper, we focus on the modeling of direct interconnection networks. Rings, n-dimensional meshes, and hypercubes are represented in tensor product form. algorithm mapping using tensor product formulation is demonstrated by mapping matrix transposition and matrix multiplication onto different networks. © 1992 IEEE.

关键词： TENSOR PRODUCT BLOCK RECURSIVE algorithm DIRECT INTERCONNECTION NETWORK algorithm mapping

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mapping of video decoder software on a VLIW DSP multiprocessor

Mapping of video decoder software on a VLIW DSP multiprocess...

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Conference on Multimedia Hardware Architectures 1998

作者： Freimann, A Brune, T Pirsch, P Informat Technol Lab D-30167 Hannover Germany

ISBN: (纸本)0819427519

When implementing today's video compression standards on programmable processors, it is essential to optimize the algorithms with respect to the underlying hardware. As an example, the core decoder functions of the H.263 hybrid coding scheme were implemented on a SIMD controlled processor with four parallel VLIW data paths, the HiPAR-DSP. The decoder tasks were implemented employing local memory, parallelization on several levels, and data statistics. Special effort was paid on the computation intensive tasks IDCT, and motion compensated frame reconstruction. To speed up the IDCT computation, a data dependent approach was chosen, which distinguishes different block types. The determination of IDCT block type could be parallelized together with other tasks, thus no additional overhead is required. Frame reconstruction mainly benefits from data parallel operations and transparent DMA transfers to and from external memory.

关键词： video decoding algorithm mapping SIMD parallelization techniques H.263 MPEG

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Event-driven Dynamic Platform Selection for Power-aware Real-time Anomaly Detection in Video

Event-driven Dynamic Platform Selection for Power-aware Real...

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9th International Conference on Computer Vision Theory and Applications (VISAPP)

作者： Blair, Calum G. Robertson, Neil M. Univ Edinburgh Inst Digital Commun Edinburgh Midlothian Scotland Heriot Watt Univ Visionlab Edinburgh Midlothian Scotland

ISBN: (纸本)9789897581335

In surveillance and scene awareness applications using power-constrained or battery-powered equipment, performance characteristics of processing hardware must be considered. We describe a novel framework for moving processing platform selection from a single design-time choice to a continuous run-time one, greatly increasing flexibility and responsiveness. Using Histogram of Oriented Gradients (HOG) object detectors and Mixture of Gaussians (MoG) motion detectors running on 3 platforms (FPGA, GPU, CPU), we characterise processing time, power consumption and accuracy of each task. Using a dynamic anomaly measure based on contextual object behaviour, we reallocate these tasks between processors to provide faster, more accurate detections when an increased anomaly level is seen, and reduced power consumption in routine or static scenes. We compare power-and speed-optimised processing arrangements with automatic event-driven platform selection, showing the power and accuracy tradeoffs between each. Real-time performance is evaluated on a parked vehicle detection scenario using the i-LIDS dataset. Automatic selection is 10% more accurate than power-optimised selection, at the cost of 12W higher average power consumption in a desktop system.

关键词： FPGA GPU Anomaly Detection Object Detection algorithm mapping

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A PN code parallel acquisition algorithm for CDMA communication and its implementation on FPGA

A PN code parallel acquisition algorithm for CDMA communicat...

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IEEE International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications

作者： Zhang, X Sun, GL ConSymp Elect Sci & Technol Co Ltd R&D Ctr Chengdu 610041 Peoples R China

A novel PN code parallel acquisition algorithm for CDMA communication is presented in the paper. Using the mapping methodology from algorithm to architecture, our algorithm is successfully implemented in FPGA chips to... 详细信息

ISBN: (纸本)0780391284

关键词： PN code parallel acquisition integrate-dump algorithm mapping digital correlator

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A Flexible Data Scheduling Scheme for Block Cipher Processor

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Procedia Computer Science 2017年 107卷 395-400页

作者： Gongli Li Jinhui Xu Zibin Dai Shoucheng Wang Yufei Zhu Institute of Information Science and Technology Zhengzhou 450001 China College of Computer & Information Engineering Henan Normal University Xinxiang 453002 China

关键词： block cipher data scheduling mode of operation algorithm mapping

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algorithm Implementation of On-Board SAR Imaging on FPGA+DSP Platform

Algorithm Implementation of On-Board SAR Imaging on FPGA+DSP...

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Signal, Information and Data Processing (ICSIDP), IEEE International Conference on

作者： Wenyue Yu Yizhuang Xie Dan Lu Bingyi Li He Chen Liang Chen Beijing Key Laboratory of Embedded Real-time Information Processing Technology Beijing Institute of Technology Beijing China Shanghai Institute of Satellite Engineering Shanghai China Beijing Institute of Technology Chongqing Innovation Center Chongqing China

ISBN: (数字)9781728123455

ISBN: (纸本)9781728123462

This paper introduces an effective parallel processing method to design the on-board SAR (Synthetic Aperture Radar) real time imaging processor using FPGA+DSP based on the high-resolution imaging algorithm. The architecture of this processor is designed based on the analysis of the algorithm operation characteristics and the inherent time relationship. In order to reduce the time consumption, pipeline and parallel joint processing method is applied. In addition, the system uses a combination of floating-point operations and fixed-point operations, which not only meets the imaging accuracy requirements but also saves the hardware scale of the system. The system requires 24s to focus the GF-3 stripmap SAR raw data with a granularity of 16384*16384 when works in 100MHz. The results demonstrate that our method was effective and the imaging quality can meet the requirements.

关键词： real-time sar imaging parallel processing architecture algorithm mapping

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Event-driven Dynamic Platform Selection for Power-aware Real-time Anomaly Detection in Video

Event-driven Dynamic Platform Selection for Power-aware Real...

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International Conference on Computer Vision Theory and Applications

作者： Calum G. Blair Neil M. Robertson Institute for Digital Communications University of Edinburgh Edinburgh U.K. Visionlab Heriot-Watt University Edinburgh U.K.

ISBN: (纸本)9781479976867

In surveillance and scene awareness applications using power-constrained or battery-powered equipment, performance characteristics of processing hardware must be considered. We describe a novel framework for moving processing platform selection from a single design-time choice to a continuous run-time one, greatly increasing flexibility and responsiveness. Using Histogram of Oriented Gradients (HOG) object detectors and Mixture of Gaussians (MoG) motion detectors running on 3 platforms (FPGA, GPU, CPU), we characterise processing time, power consumption and accuracy of each task. Using a dynamic anomaly measure based on contextual object behaviour, we reallocate these tasks between processors to provide faster, more accurate detections when an increased anomaly level is seen, and reduced power consumption in routine or static scenes. We compare power- and speed- optimised processing arrangements with automatic event-driven platform selection, showing the power and accuracy tradeoffs between each. Real-time performance is evaluated on a parked vehicle detection scenario using the i-LIDS dataset. Automatic selection is 10% more accurate than power-optimised selection, at the cost of 12W higher average power consumption in a desktop system.

关键词： FPGA GPU Anomaly Detection Object Detection algorithm mapping

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