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An FPGA-Based Event-Driven SNN Accelerator for DVS Applications With Structured Sparsity and Early-Stop

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Cheng, Xi Cao, Shu Wang, Shangmei Wang, Mingyu Li, Wenhong Zeng, Xiaoyang Fudan Univ State Key Lab Integrated Chips & Syst Shanghai 201203 Peoples R China

This paper proposed an algorithm-hardware co-design of an event-driven spiking neural network (SNN) accelerator for classification tasks of event-based data from dynamic vision sensors (DVS), which can implement a feed-forward SNN with a maximum network size of 1 million synapses. configurable structured sparsity is introduced between the first layer and the second layer to improve energy efficiency and balance the workload between different processing elements (PEs). The number of available neurons in the accelerator is sparsity-dependent and ranges from 1024 to 4096. The modified leaky-integrate-fire (LIF) neuron model and an event-driven neuron update scheme are employed in both algorithm and hardware to fully utilize the natural sparsity of DVS event stream. Early-stop inference strategy on the hardware enables a trade-off between inference accuracy and efficiency. A three-layer fully connected SNN is trained through backpropagation through time (BPTT) and is implemented and evaluated on Xilinx ZCU104 FPGA. Our design can achieve 96.0% accuracy on the N-MNIST dataset and 79.0% accuracy on the DVS128-Gesture dataset both at 50% sparsity. The top performance of the accelerator on ZCU104 is 3.22 GSOP/S and 3.99 GSOP/W at 250 MHz.

关键词： Spiking neural networks dynamic vision sensors algorithm-hardware co-design event-driven structured sparsity FPGAs

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algorithm-hardware co-optimization for Energy-efficient Drone Detection on Resource-constrained FPGA

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ACM TRANSACTIONS ON REcoNFIGURABLE TECHNOLOGY AND SYSTEMS 2023年第2期16卷 1-25页

作者： Suh, Han-Sok Meng, Jian Nguyen, Ty Kumar, Vijay Cao, Yu Seo, Jae-Sun Arizona State Univ 781 E Terrace RdISTB4 591 Tempe AZ 85287 USA Univ Penn 220 S 33rd St Philadelphia PA 19104 USA

convolutional neural network (CNN)-based object detection has achieved very high accuracy;e.g., singleshot multi-box detectors (SSDs) can efficiently detect and localize various objects in an input image. However, they require a high amount of computation and memory storage, which makes it difficult to perform efficient inference on resource-constrained hardware devices such as drones or unmanned aerial vehicles (UAVs). Drone/UAV detection is an important task for applications including surveillance, defense, and multidrone self-localization and formation control. In this article, we designed and co-optimized an algorithm and hardware for energy-efficient drone detection on resource-constrained FPGA devices. We trained an SSD object detection algorithm with a custom drone dataset. For inference, we employed low-precision quantization and adapted the width of the SSD CNN model. To improve throughput, we use dual-data rate operations for DSPs to effectively double the throughput with limited DSP counts. For different SSD algorithm models, we analyze accuracy or mean average precision (mAP) and evaluate the corresponding FPGA hardware utilization, DRAM communication, and throughput optimization. We evaluated the FPGA hardware for a custom drone dataset, Pascal VOC, and coco2017. Our proposed design achieves a high mAP of 88.42% on the multi-drone dataset, with a high energy efficiency of 79 GOPS/W and throughput of 158 GOPS using the Xilinx Zynq ZU3EG FPGA device on the Open Vision computer version 3 (OVC3) platform. Our design achieves 1.1 to 8.7x higher energy efficiency than prior works that used the same Pascal VOC dataset, using the same FPGA device, but at a low-power consumption of 2.54W. For the coco dataset, our MobileNet-V1 implementation achieved an mAP of 16.8, and 4.9 FPS/W for energy-efficiency, which is similar to 1.9x higher than prior FPGA works or other commercial hardware platforms.

关键词： FPGA accelerator object detection algorithm-hardware co-design neural networks

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A coNCEPT FOR A SLAM BACK END hardware ACCELERATOR 49

A CONCEPT FOR A SLAM BACK END HARDWARE ACCELERATOR

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49th IEEE International conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Henningson, Toivo Adalbjornsson, Stefan Berkeman, Anders Drougge, Carl Erickson, Xavante Hunt, Alexander Ericsson Res Lund Sweden

ISBN: (纸本)9798350344868;9798350344851

This research aims to develop energy-efficient hardware accelerators for Simultaneous Location And Mapping (SLAM) back end applications by employing algorithm-hardware co-design. Utilizing the iSAM2 algorithm, which uses graphical modeling to solve iterative Gauss-Newton problems, we continuously update maps by incorporating solutions from previous iterations or timesteps. We address the performance bottleneck arising from memory writes of intermediate results by modifying the original algorithm. Additionally, we analyze the algorithm's parallelizability to meet latency demands. These hardware accelerators are designed as Intellectual Property (IP) blocks, suitable for integration into custom Systems-on-Chip (SoC). We evaluate the design using both holistic and block-level metrics, focusing on latency and energy efficiency. This work has implications for energy-constrained devices like drones and Extended Reality (XR) devices.

关键词： algorithm-hardware co-design energy constrained devices hardware accelerator SLAM back end iterative sparse Cholesky IP blocks

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algorithm-hardware co-Optimization for Energy-Efficient Drone Detection on Resource-constrained FPGA 20

Algorithm-Hardware Co-Optimization for Energy-Efficient Dron...

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20th International conference on Field-Programmable Technology (ICFPT)

作者： Suh, Han-sok Meng, Jian Ty Nguyen Venkataramanaiah, Shreyas K. Kumar, Vijay Cao, Yu Seo, Jae-sun Arizona State Univ Tempe AZ 85287 USA Univ Penn Philadelphia PA 19104 USA

ISBN: (纸本)9781665420105

convolutional neural network (CNN) based object detection has achieved very high accuracy, e.g. single-shot multibox detectors (SSD) can efficiently detect and localize various objects in an input image. However, they require a high amount of computation and memory storage, which makes it difficult to perform efficient inference on resource-constrained hardware devices such as drones or unmanned aerial vehicles (UAVs). Drone/UAV detection is an important task for applications including surveillance, defense, and multi-drone self-localization and formation control. In this paper, we designed and co-optimized algorithm and hardware for energy-efficient drone detection on resource-constrained FPGA devices. We trained SSD object detection algorithm with a custom drone dataset. For inference, we employed low-precision quantization and adapted the width of the SSD CNN model. To improve throughput, we use dual-data rate operations for DSPs to effectively double the throughput with limited DSP counts. For different SSD algorithm models, we analyze accuracy or mean average precision (mAP) and evaluate the corresponding FPGA hardware utilization, DRAM communication, throughput optimization. Our proposed design achieves a high mAP of 88.42% on the multi-drone dataset, with a high energy-efficiency of 79 GOPS/VV and throughput of 158 GOPS using Xilinx Zynq ZU3EG FPGA device on the Open Vision computer version 3 (OVC3) platform. Our design achieves 2.7X higher energy efficiency than prior works using the same FPGA device, at a low-power consumption of 1.98 W.

关键词： FPGA accelerator convolutional neural network object detection algorithm-hardware co-design

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NASA-F: FPGA-Oriented Search and Acceleration for Multiplication-Reduced Hybrid Networks

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第1期71卷 306-319页

作者： Shi, Huihong Xu, Yang Wang, Yuefei Mao, Wendong Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China Sun Yat sen Univ Sch Integrated Circuits Shenzhen 518107 Peoples R China

The costly multiplications challenge the deployment of modern deep neural networks (DNNs) on resource-constrained devices. To promote hardware efficiency, prior works have built multiplication-free models. However, they are generally inferior to their multiplication-based counterparts in accuracy, calling for multiplication-reduced hybrid models to marry the benefits of both approaches. To achieve this goal, recent works, i.e., NASA and NASA+ , have developed Neural Architecture Search (NAS) and Acceleration frameworks to search for and accelerate such hybrid models via a tailored differentiable NAS (DNAS) engine and dedicated ASIC-based accelerators. In this paper, we delve deeper into the inherent advantages of FPGAs and present an enhanced approach called NASA-F, which focuses on FPGA-oriented search and acceleration for hybrid models. Specifically, on the algorithm level, we develop a tailored one-shot supernet-based NAS engine to streamline the search for hybrid models, eliminating the need for executing NAS for each deployment as well as additional training/finetuning steps. On the hardware level, we develop a chunk-based accelerator to fully leverage the diverse hardware resources available on FPGAs for the acceleration of heterogeneous layers in hybrid models, aiming to enhance both hardware utilization and throughput. Extensive experimental results consistently validate the superiority of our NASA-F framework, e.g., we can gain up arrow 0.67% top-1 accuracy over the prior work NASA on CIFAR100 even without additional training steps for searched models. Additionally, we can achieve up to up arrow 1.86x throughout and up arrow 2.16x FPS with up arrow 0.39% top-1 accuracy over the state-of-the-art multiplication-based system on Tiny-ImageNet. codes are available at https://***/shihuihong214/NASA-F.

关键词： Multiplication-reduced hybrid networks neural architecture search chunk-based accelerator FPGA accelerator algorithm-hardware co-design

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NASA plus : Neural Architecture Search and Acceleration for Multiplication-Reduced Hybrid Networks

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2023年第6期70卷 2523-2536页

作者： Shi, Huihong You, Haoran Wang, Zhongfeng Lin, Yingyan Georgia Inst Technol Atlanta GA 30332 USA Nanjing Univ Sch Elect Sci & Engn Nanjing 210093 Peoples R China Georgia Inst Technol Sch Comp Sci Atlanta GA 30332 USA Nanjing Univ Sch Elect Sci & Engn Nanjing 210093 Peoples R China

Multiplication is arguably the most computation-intensive operation in modern deep neural networks (DNNs), limiting their extensive deployment on resource-constrained devices. Thereby, pioneering works have handcrafted multiplication-free DNNs, which are hardware-efficient but generally inferior to their multiplication-based counterparts in task accuracy, calling for multiplication-reduced hybrid DNNs to marry the best of both worlds. To this end, we propose a Neural Architecture Search and Acceleration (NASA) framework for the above hybrid models, dubbed NASA+, to boost both task accuracy and hardware efficiency. Specifically, NASA+ augments the state-of-the-art (SOTA) search space with multiplication-free operators to construct hybrid ones, and then adopts a novel progressive pretraining strategy to enable the effective search. Furthermore, NASA+ develops a chunk-based accelerator with novel reconfigurable processing elements to better support searched hybrid models, and integrates an auto-mapper to search for optimal dataflows. Experimental results and ablation studies consistently validate the effectiveness of our NASA+ algorithm-hardware co-design framework, e.g., we can achieve up to 65.1% lower energy-delay-product with comparable accuracy over the SOTA multiplication-based system on CIFAR100. codes are available at https://***/GATECH-EIC/NASA.

关键词： Multiplication-reduced hybrid networks neural architecture search chunk-based accelerator reconfigurable PE algorithm-hardware co-design

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BSViT: A Bit-Serial Vision Transformer Accelerator Exploiting Dynamic Patch and Weight Bit-Group Quantization

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第9期71卷 4064-4077页

作者： Wang, Gang Cai, Siqi Li, Wenjie Lyu, Dongxu He, Guanghui Shanghai Jiao Tong Univ Sch Elect Informat & Elect Engn Shanghai 200240 Peoples R China Shanghai Jiao Tong Univ AI Inst MoE Key Lab Artificial Intelligence Shanghai 200240 Peoples R China

Vision Transformers (ViTs) have achieved remark-able success in computer vision (CV) and are increasingly recognized as the new backbone for vision-language multi-modal tasks. Despite their success, the high computational cost associated with ViTs hinders their inference efficiency. In this paper, we introduce BSViT, a bit-serial Vision Transformer accelerator enhanced by algorithm-hardware co-design. BSViT can efficiently accelerate both plain and hierarchical Vision Transformer inference. At the algorithm level, we propose a post-training quantization scheme named dynamic patch and weight bit-group quantization. We first introduce a dynamic patch quantization (DPQ) scheme to dynamically allocate bit-width to different image patches based on their importance, thus reducing bit width and saving computation without significantly impacting accuracy. Second, we propose a weight bit-group quantization (BGQ)scheme to evenly distribute bits within groups and achieve workload balance across processing elements (PEs). At the hardware level, we propose a term-separate bit-serial accelerator to efficiently support DPQ and BGQ. We introduce dense and sparse bit-serial PEs to manipulate the dense least significant term (LST) and sparse most significant term (MST) work loads. A dense-sparse hybrid dataflow is devised to efficiently balance the two kinds of workloads. Our experiments show that BSViT can achieve up to 1.95x speedup and 2.72x energy efficiency compared to state-of-the-art (SOTA) bit-serial accelerators and achieve up to 3.69x energy efficiency compared to SOTA Trans-former accelerators.

关键词： Transformers Quantization (signal) computer architecture Training hardware Accuracy Heuristic algorithms Vision transformer bit serial algorithm-hardware co-design post-training quantization dense-sparse hybrid dataflow

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An Energy-Efficient ECG Processor With Ultra-Low-Parameter Multistage Neural Network and Optimized Power-of-Two Quantization

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 2024年第6期18卷 1296-1307页

作者： Zhang, Zuo Guan, Yunqi Ye, Wenbin Shenzhen Univ Sch Microscale Optoelect Shenzhen 518060 Peoples R China Shenzhen Univ Coll Elect & Informat Engn Shenzhen 518060 Peoples R China

This work presents an energy-efficient ECG processor designed for Cardiac Arrhythmia Classification. The processor integrates a pre-processing and neural network accelerator, achieved through algorithm-hardware co-design to optimize hardware resources. We propose a lightweight two-stage neural network architecture, where the first stage includes discrete wavelet transform and an ultra-low-parameter multilayer perceptron (MLP) network, and the second stage utilizes group convolution and channel shuffle. Both stages leverage neural networks for hardware resource reuse and feature a reconfigurable processing element array and memory blocks adapted to the proposed two-stage structure to efficiently handle various convolution and MLP layers operations in the two-stage network. Additionally, an optimized power-of-two (OPOT) quantization technique is proposed to enhance accuracy in low-bit quantization, and a multiplier-less processing element structure tailored for the OPOT weight quantization is introduced. The ECG processor was implemented on a 65nm CMOS process technology with 4KB of SRAM memory, achieving an energy consumption per inference of 0.15 uJ with a power supply of 1V, 64% energy saving compared to the recent state-of-the-art work. Under 4-bit weight precision, the 5-class ECG signal classification accuracy reached 98.59% on the MIT-BIH arrhythmia dataset.

关键词： Electrocardiography Neural networks Discrete wavelet transforms Heart beat Quantization (signal) convolution hardware ECG processor energy-efficient neural network low-bit quantization algorithm-hardware co-design

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Accelerating On-Device DNN Training Workloads via Runtime convergence Monitor

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IEEE TRANSACTIONS ON coMPUTER-AIDED design OF INTEGRATED CIRCUITS AND SYSTEMS 2023年第5期42卷 1574-1587页

作者： Choi, Seungkyu Shin, Jaekang Kim, Lee-Sup Univ Michigan Dept Elect & Comp Engn Ann Arbor MI 48109 USA Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon 34141 South Korea

With the growing demand for processing deep learning applications on edge devices, on-device DNN training has become a major workload to execute a variety of vision tasks suited for users. Therefore, architectures employed with algorithm co-design to accelerate the training process have been steadily studied. However, previous solutions are mostly supported by extended versions of the inference studies, such as sparsity, data flow, quantization, etc. Moreover, most works examine their schemes on from-the-scratch training that cannot tolerate inaccurate computing. Accordingly, there are still factors that hinder the overall speed of the DNN training process that has not been addressed in practical workloads. In this work, we propose a runtime convergence monitor to achieve massive computational savings in the practical on-device training workloads (i.e., transfer-learning-based task adaptation). By monitoring the network output data, we determine the training intensity of incoming tasks and adaptively detect the convergence in iteration intervals for training diverse datasets. Furthermore, we enable the computation skip of converged images determined by the monitored prediction probability to enhance the training speed within an iteration. As a result, we perform an accurate but fast convergence in model training for the task adaptation with minimal overhead. Unlike the previous approximation methods, our monitoring system enables runtime optimization and can be easily applicable to any type of accelerator attaining significant speedup. Evaluation results on various datasets show geomean of 2.2x speedup when applied in any systolic architectures and further enhancement of 3.6x when applied in accelerators dedicated for on-device training.

关键词： algorithm-hardware co-design deep learning on-device training training convergence transfer learning

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An Ultralow-Power H.264/AVC Intra-Frame Image compression Accelerator for Intelligent Event-Driven IoT Imaging Systems

IEEE SOLID-STATE CIRCUITS LETTERS

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IEEE SOLID-STATE CIRCUITS LETTERS 2024年 7卷 30-33页

作者： Zhang, Qirui An, Hyochan Bejarano-Carbo, Andrea Kim, Hun-Seok Blaauw, David Sylvester, Dennis Univ Michigan Dept Elect & Comp Engn Ann Arbor MI 48109 USA Apple Cupertino CA 95014 USA

This letter presents an ultralow-power (ULP) H.264/AVCintra-frame image compression accelerator tailored for intelligent event-driven ULP IoT imaging systems. The H.264/AVC intra-frame codec is customized to enable compression of arbitrary nonrectangular change-detected regions. To optimize energy and latency from image memory accesses, novel algorithm-hardware co-designs are proposed for intra-frame predictions, reducing overhead for neighbor macroblock (McB)accesses by 2.6xat a negligible quality loss. With split control for major processing phases, latency is optimized by exploiting data dependency and pipelining. Area and leakage of major computation units are reduced through data path micro-architecture reconfiguration. Fabricated in40 nm, it occupies a mere 0.32 mm2area with 4-kB SRAM. At 0.6 V and153 kHz, it consumes only 1.21 mu W, with 30.9 pJ/pixel compression energy efficiency that rivals state-of-the-art designs. For an event-driven IoT imaging system, the combination of the proposed accelerator and change detection brings 133xreduction to the overall energy for regressing an image of change-detected region of interest

关键词： algorithm-hardware co-design event-driven imaging system H.264/AVC intra-frame coding hardware accelerator ultralow-power (ULP)

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