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检索条件"主题词=Algorithm-Hardware Co-Design"
37 条 记 录,以下是31-40 订阅
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DUAL: Acceleration of Clustering algorithms using Digital-based Processing In-Memory  53
DUAL: Acceleration of Clustering Algorithms using Digital-ba...
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53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
作者: Imani, Mohsen Pampana, Saikishan Gupta, Saransh Zhou, Minxuan Kim, Yeseong Rosing, Tajana UC Irvine Dept Comp Sci Irvine CA 92697 USA DGIST Dept Informat & Commun Engn Daegu South Korea Univ Calif San Diego Dept Comp Sci & Engn San Diego CA USA
Today's applications generate a large amount of data that need to be processed by learning algorithms. In practice, the majority of the data are not associated with any labels. Unsupervised learning, i.e., cluster... 详细信息
来源: 评论
Efficient Network construction Through Structural Plasticity
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IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS 2019年 第3期9卷 453-464页
作者: Du, Xiaocong Li, Zheng Ma, Yufei Cao, Yu Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Arizona State Univ Sch Comp Informat & Decis Syst Engn Tempe AZ 85287 USA
Deep Neural Networks (DNNs) on hardware is facing excessive computation cost due to the massive number of parameters. A typical training pipeline to mitigate over-parameterization is to pre-define a DNN structure with... 详细信息
来源: 评论
Efficient Network construction Through Structural Plasticity
Efficient Network Construction Through Structural Plasticity
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1st AI compute Symposium (AICS)
作者: Du, Xiaocong Li, Zheng Ma, Yufei Cao, Yu Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Arizona State Univ Sch Comp Informat & Decis Syst Engn Tempe AZ 85287 USA
Deep Neural Networks (DNNs) on hardware is facing excessive computation cost due to the massive number of parameters. A typical training pipeline to mitigate over-parameterization is to pre-define a DNN structure with... 详细信息
来源: 评论
Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating  52
Boosting the Performance of CNN Accelerators with Dynamic Fi...
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52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
作者: Hua, Weizhe Zhou, Yuan De Sa, Christopher Zhang, Zhiru Suh, G. Edward Cornell Univ Ithaca NY 14850 USA
This paper proposes a new fine-grained dynamic pruning technique for CNN inference, named channel gating, and presents an accelerator architecture that can effectively exploit the dynamic sparsity. Intuitively, channe... 详细信息
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MnnFast: A Fast and Scalable System Architecture for Memory-Augmented Neural Networks  19
MnnFast: A Fast and Scalable System Architecture for Memory-...
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46th International Symposium on computer Architecture (ISCA) / Workshop on computer Architecture Education (WCAE)
作者: Jang, Hanhwi Kim, Joonsung Jo, Jae-Eon Lee, Jaewon Kim, Jangwoo POSTECH Pohang Dept Comp Sci & Engn Pohang South Korea Seoul Natl Univ Dept Elect & Comp Engn Seoul South Korea
Memory-augmented neural networks are getting more attention from many researchers as they can make an inference with the previous history stored in memory. Especially, among these memory-augmented neural networks, mem... 详细信息
来源: 评论
The Mondrian Data Engine  17
The Mondrian Data Engine
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44th Annual International Symposium on computer Architecture (ISCA)
作者: Drumond, Mario Daglis, Alexandros Mirzadeh, Nooshin Ustiugov, Dmitrii Picorel, Javier Falsafi, Babak Grot, Boris Pnevmatikatos, Dionisios Ecole Polytech Fed Lausanne EcoCloud Lausanne Switzerland Univ Edinburgh Edinburgh Midlothian Scotland FORTH ICS & ECE TUC Edinburgh Midlothian Scotland
The increasing demand for extracting value out of ever-growing data poses an ongoing challenge to system designers, a task only made trickier by the end of Dennard scaling. As the performance density of traditional CP... 详细信息
来源: 评论
EIE: Efficient Inference Engine on compressed Deep Neural Network  16
EIE: Efficient Inference Engine on Compressed Deep Neural Ne...
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43rd ACM/IEEE Annual International Symposium on computer Architecture (ISCA)
作者: Han, Song Liu, Xingyu Mao, Huizi Pu, Jing Pedram, Ardavan Horowitz, Mark A. Dally, William J. Stanford Univ Stanford CA 94305 USA NVIDIA Santa Clara CA USA
State-of-the-art deep neural networks (DNNs) have hundreds of millions of connections and are both computationally and memory intensive, making them difficult to deploy on embedded systems with limited hardware resour... 详细信息
来源: 评论