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Tiled architecture of a CNN-mostly IP System

Tiled Architecture of a CNN-mostly IP System

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Conference on VLSI Circuits and Systems IV

作者： Spaanenburg, Lambert Malki, Suleyman Lund Univ Elect & Informat Technol Dept S-22100 Lund Sweden

ISBN: (纸本)9780819476371

Multi-core architectures have been popularized with the advent of the IBM CELL. On a finer grain the problems in scheduling multi-cores have already existed in the tiled architectures, such as the EPIC and Da Vinci. It is not easy to evaluate the performance of a schedule on such architecture as historical data are not available. One solution is to compile algorithms for which an optimal schedule is known by analysis. A typical example is an algorithm that is already defined in terms of many collaborating simple nodes, such as a Cellular Neural Network (CNN). A simple node with a local register stack together with a 'rotating wheel' internal communication mechanism has been proposed. Though the basic CNN allows for a tiled implementation of a tiled algorithm on a tiled structure, a practical CNN system will have to disturb this regularity by the additional need for arithmetical and logical operations. Arithmetic operations are needed for instance to accommodate for low-level image processing, while logical operations are needed to fork and merge different data streams without use of the external memory. It is found that the 'rotating wheel' internal communication mechanism still handles such mechanisms without the need for global control. Overall the CNN system provides for a practical network size as implemented on a FPGA, can be easily used as embedded IP and provides a clear benchmark for a multi-core compiler.

关键词： Behavioral Synthesis algorithm-specific architecture Cellular Neural Network Field-Programmable Gate-Array multi-core benchmark

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Optimization of Input-Constrained Systems

Optimization of Input-Constrained Systems

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Conference on VLSI Circuits and Systems IV

作者： Malki, Suleyman Spaanenburg, Lambert Lund Univ LTH Dept Informat Technol Lund Sweden

ISBN: (纸本)9780819476371

The computational demands of algorithms are rapidly growing. The naive implementation uses extended double-precision floating-point numbers and has therefore extreme difficulties in maintaining real-time performance. For fixed-point numbers, the value representation pushes in two directions (value range and step size) to set the application-dependent word size. In the general case, checking all combinations of all different values on all system inputs will easily become computationally infeasible. Checking corner cases only helps to reduce the combinatorial explosion, as still checking for accuracy and precision to limit word size remains a considerable effort. A range of evolutionary techniques have been tried where the sheer size of the problem withstands an extensive search. When the value range can be limited, the problem becomes tractable and a constructive approach becomes feasible. We propose an approach that is reminiscent of the *** logic minimization procedure. Next to the conjunctive search as popular in Boolean minimization, we investigate the disjunctive approach that starts from a presumed minimal word size. To eliminate the occurrence of anomalies, this still has to be checked for larger word sizes. The procedure has initially been implemented using Java and Mat lab. We have applied the above procedure to feed-forward and to cellular neural networks (CNN) as typical examples of input-constrained systems. In the case of hole-filling by means of a CNN, we find that the 1461 different coefficient sets can be reduced to 360, each giving robust behaviour on 7-bits internal words.

关键词： Behavioural Synthesis algorithm-specific architecture Fixed Number Representation Field-Programmable Gate-Array

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3D-design exploration of CNN algorithms

3D-design exploration of CNN algorithms

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Conference on VLSI Circuits and Systems V

作者： Spaanenburg, Lambert Malki, Suleyman Lund Univ Dept EIT S-22100 Lund Sweden

ISBN: (纸本)9780819486561

Multi-dimensional algorithms are hard to implement on classical platforms. Pipelining may exploit instruction-level parallelism, but not in the presence of simultaneous data;threads optimize only within the given restrictions. Tiled architectures do add a dimension to the solution space. With locally a large register store, data parallelism is handled, but only to a dimension. 3-D technologies are meant to add a dimension in the realization. Applied on the device level, it makes each computational node smaller. The interconnections become shorter and hence the network will be condensed. Such advantages will be easily lost at higher implementation levels unless 3-D technologies as multi-cores or chip stacking are also introduced. 3-D technologies scale in space, where (partial) reconfiguration scales in time. The optimal selection over the various implementation levels is algorithm dependent. The paper discusses such principles while applied on the scaling of cellular neural networks (CNN). It illustrates how stacking of reconfigurable chips supports many algorithmic requirements in a defect-insensitive manner. Further the paper explores the potential of chip stacking for multi-modal implementations in a reconfigurable approach to heterogeneous architectures for algorithm domains.

关键词： Behavioral Synthesis algorithm-specific architecture Cellular Neural Network Field-Programmable Gate-Array multi-core benchmark

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