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FPGA-Based Real-Time Implementation of Detection Algorithm for Automatic Traffic Surveillance Sensor Network

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2012年第1期68卷 1-18页

作者： Wojcikowski, Marek Zaglewski, Robert Pankiewicz, Bogdan Gdansk Univ Technol Gdansk Poland Intel Shannon Ltd Shannon Ireland

This paper describes the FPGA-based hardware implementation of an algorithm for an automatic traffic surveillance sensor network. The aim of the algorithm is to extract moving vehicles from real-time camera images for the evaluation of traffic parameters, such as the number of vehicles, their direction of movement and their approximate speed, using low power hardware of a sensor network node. A single, stationary, monochrome camera is used, mounted at a location high above the road. Occlusions are not detected, however simple shadow and highlight elimination is performed. The algorithm is designed for frame-rate efficiency and is specially suited for pipelined hardware implementation. The authors, apart from the careful selection of particular steps of the algorithm and the modifications towards parallel implementation, also proposed novel improvements such as backgrounds' binary mask combination or non-linear functions in highlight detection, resulting in increasing the robustness and efficiency of hardware realization. The algorithm has been implemented in FPGA and tested on real-time video streams from an outdoor camera.

关键词： algorithms implemented in hardware Image-processing hardware Video analysis Sensor networks

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hardware implementation trade-offs of polynomial approximations and interpolations

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IEEE TRANSACTIONS ON COMPUTERS 2008年第5期57卷 686-701页

作者： Lee, Dong-U Cheung, Ray C. C. Luk, Wayne Villasenor, John D. Mojix Inc Los Angeles CA 90025 USA Univ London Imperial Coll Sci Technol & Med Dept Comp London England Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA

This paper examines the hardware implementation trade-offs when evaluating functions via piecewise polynomial approximations and interpolations for precisions of up to 24 bits. In polynomial approximations, polynomials are evaluated using stored coefficients. Polynomial interpolations, however, require the coefficients to be computed on-the-fly by using stored function values. Although it is known that interpolations require less memory than approximations, but at the expense of additional computations, the trade-offs in memory, area, delay, and power consumption between the two approaches have not been examined in detail. This work quantitatively analyzes these trade-offs for optimized approximations and interpolations across different functions and target precisions. hardware architectures for degree-1 and degree-2 approximations and interpolations are described. The results show that the extent of memory savings realized by using interpolation is significantly lower than what is commonly believed. Furthermore, experimental results on a field-programmable gate array (FPGA) show that, for high output precision, degree-1 interpolations offer considerable area and power savings over degree-1 approximations, but similar savings are not realized when degree-2 interpolations and approximations are compared. The availability of both interpolation-based and approximation-based designs offers a richer set of design trade-offs than what is available using either interpolation or approximation alone.

关键词： algorithms implemented in hardware interpolation approximation VLSI systems

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A new solution to the hyperbolic tangent implementation in hardware: polynomial modeling of the fractional exponential part

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NEURAL COMPUTING & APPLICATIONS 2013年第2期23卷 363-369页

作者： Nascimento, Ivo Jardim, Ricardo Morgado-Dias, Fernando Univ Madeira Competence Ctr Exact Sci & Engn P-9000390 Funchal Portugal Univ Madeira Madeira Interact Technol Inst P-9000390 Funchal Portugal

The most difficult part of an artificial neural network to implement in hardware is the nonlinear activation function. For most implementations, the function used is the hyperbolic tangent. This function has received much attention in relation to hardware implementation. Nevertheless, there is no consensus regarding the best solution. In this paper, we propose a new approach by implementing the hyperbolic tangent in hardware with a polynomial modeling of the fractional exponential part. The results in the paper then demonstrate, through the use of an example, that this solution is faster than the CORDIC algorithm, but slower than the piecewise linear solution with the same error. The advantage over the piecewise linear approach is that it uses less memory.

关键词： algorithms implemented in hardware Gate arrays hardware description languages Neural networks CORDIC

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A hardware Gaussian noise generator using the Box-Muller method and its error analysis

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IEEE TRANSACTIONS ON COMPUTERS 2006年第6期55卷 659-671页

作者： Lee, DU Villasenor, JD Luk, W Leong, PHW Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA Univ London Imperial Coll Sci Technol & Med Dept Comp London SW7 2AZ England Chinese Univ Hong Kong Dept Comp Sci & Engn Shatin Hong Kong Peoples R China

We present a hardware Gaussian noise generator based on the Box-Muller method that provides highly accurate noise samples. The noise generator can be used as a key component in a hardware-based simulation system, such as for exploring channel code behavior at very low bit error rates, as low as 10(-12) to 10(-13). The main novelties of this work are accurate analytical error analysis and bit-width optimization for the elementary functions involved in the Box-Muller method. Two 16-bit noise samples are generated every clock cycle and, due to the accurate error analysis, every sample is analytically guaranteed to be accurate to one unit in the last place. An implementation on a Xilinx Virtex-4 XC4VLX100-12 FPGA occupies 1,452 slices, three block RAMs, and 12 DSP slices, and is capable of generating 750 million samples per second at a clock speed of 375 MHz. The performance can be improved by exploiting concurrent execution: 37 parallel instances of the noise generator at 95 MHz on a Xilinx Virtex-II Pro XC2VP100-7 FPGA generate seven billion samples per second and can run over 200 times faster than the output produced by software running on an Intel Pentium-4 3 GHz PC. The noise generator is currently being used at the Jet Propulsion Laboratory, NASA to evaluate the performance of low-density parity-check codes for deep-space communications.

关键词： algorithms implemented in hardware computer arithmetic error analysis elementary function approximation field programmable gate arrays minimax approximation and algorithms optimization random number generation simulation

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GAARP: A power-aware GALS architecture for real-time algorithm-specific tasks

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IEEE TRANSACTIONS ON COMPUTERS 2005年第6期54卷 752-766页

作者： Bhunia, S Datta, A Banerjee, N Roy, K Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47906 USA

Reducing the energy consumption of a real-time system has emerged as an important design concern. In this paper, we propose GAARP, an adaptive scalable architecture targeted toward algorithm-specific tasks for just-in-time performance using the right amount of power. The architecture consists of Globally Asynchronous and Locally Synchronous ( GALS) building blocks, where the processing hardware is realized by a set of smaller slices of similar structure, each running synchronously with independent clocks. We demonstrate that, for different real-time commercial applications with algorithm-specific jobs like online transaction processing, digital filtering, Fourier transform, etc., the proposed architecture allows dynamic load-balancing and adaptive intertask voltage scaling based on the load in each of the processing units. Compared to a synchronous implementation of the same functionality, we show that the proposed hardware can achieve higher efficiency in terms of power and performance by exploiting the flexibility to balance the load and change the supply voltage. The architecture also lends itself to process tolerance since it can detect process-shifts for the individual processing units and determine the appropriate operating voltage/frequency for each unit. Simulation results for two representative applications show that, for a modest system configuration and random job distribution, we obtain up to 67 percent improvement in MOPS/W ( millions of operations per second per watt) over a fully synchronous implementation.

关键词： asynchronous/synchronous operations algorithms implemented in hardware fault tolerance energy-aware systems

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High-Speed algorithms and Architectures for Range Reduction Computation

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2011年第3期19卷 512-516页

作者： Jaime, Francisco J. Sanchez, Miguel A. Hormigo, Javier Villalba, Julio Zapata, Emilio L. Univ Malaga Comp Architecture Dept E-29071 Malaga Spain

Range reduction is a crucial step for accuracy in trigonometric functions evaluation. This paper shows and compares a set of algorithms for additive range reduction computation and their corresponding application-specific integrated circuit implementations (ensuring an accuracy of one unit in the last place). A word-serial architecture implementation has been used as a reference for clearer comparisons. Besides, a new table-based pipelined architecture for range reduction has also been proposed.

关键词： algorithms algorithms implemented in hardware computer arithmetic cost/performance elementary function approximation pipeline

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Leveraging Modern C plus plus in High-Level Synthesis

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2023年第4期42卷 1123-1132页

作者： Lahti, Sakari Rintala, Matti Hamalainen, Timo D. Tampere Univ Unit Comp Sci Tampere 33720 Finland

High-level synthesis (HLS) enables the automated conversion of high-level language algorithms into synthesizable register-transfer level code, allowing computation-intensive algorithms to be accelerated on FPGAs. Most HLS tools have C++ as their input language, as it is widely known in both software and hardware industry. However, even though C++ receives a new standard every three years, the HLS tool vendors have mostly provided support and examples using C++98/03. Limiting to early C++ standards imposes a productivity penalty, since the newer standards provide both compilation time reductions and more concise, expressive, and maintainable way of writing code. In this study, we make the case for adopting modern C++ in HLS. We inspect the language features of C++11 and forward, and consider their benefits for HLS. We also test the present support for the modern language features with two state-of-the-art commercial HLS tools. Finally, we provide an extended example, demonstrating the increased clarity of code achieved using the newer standards. We note that the investigated HLS tools already have good support for modern C++ features, and urge their adoption to increase designer productivity.

关键词： C plus plus languages Codes hardware Software Productivity Standards Software algorithms algorithms implemented in hardware C plus plus language high-level synthesis (HLS) reconfigurable hardware

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An embedded co-processor for accelerating window joins over uncertain data streams

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MICROPROCESSORS AND MICROSYSTEMS 2012年第6期36卷 489-504页

作者： Qian, Jiangbo Li, Youming Wang, Yongli Chen, Huahui Dong, Yihong Ningbo Univ Sch Informat Sci & Engn Ningbo 315211 Zhejiang Peoples R China Nanjing Univ Sci & Technol Sch Comp Sci & Technol Nanjing 210094 Jiangsu Peoples R China

In many new applications fields, such as surveillance, networks, and sensor technologies, the generating data are time-varying, unpredictable, uncertain, continuously arriving, and must be processed online. To keep up with these rapid data streams, accelerating data processing is one of the key problems in a UDSMS (Uncertain Data Stream Management System). Most of the algorithms that are proposed in the literature are implemented in software and can potentially result in CPU saturation. To greatly promote UDSMS processing speed, we focus on accelerating join processing, which is one of the most costly operations. We propose, for the first time, a hardware co-processor called UWJSP (Uncertain data Window Join Special co-Processor) for implementation. UWJSP is composed of several processing units. Each unit executes special instructions that continuously track changing queries. We also propose an integrated method for improving the scalability and flexibility. The experimental results reveal that UWJSP can achieve an order of magnitude improvement over a software implementation. The low cost and high performance UWJSP can be used in applications where real-time performance is indispensable. (C) 2012 Elsevier B.V. All rights reserved.

关键词： algorithms implemented in hardware High-speed arithmetic Logic design Query processing

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Word-Based Montgomery Modular Multiplication Algorithm for Low-Latency Scalable Architectures

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IEEE TRANSACTIONS ON COMPUTERS 2010年第8期59卷 1145-1151页

作者： Shieh, Ming-Der Lin, Wen-Ching Natl Cheng Kung Univ Dept Elect Engn Tainan 70101 Taiwan

Modular multiplication is a crucial operation in public key cryptosystems like RSA and elliptic curve cryptography (ECC). This paper presents a new word-based Montgomery modular multiplication algorithm which can be used to achieve a low-latency scalable architecture for efficient hardware implementations. We show how to relax the data dependency in conventional word-based algorithms so that a latency of exactly one cycle can be obtained regardless of the chosen word size w(w > 1). With the presented operand reduction scheme, the proposed scalable architecture can operate at high speeds and suitable data paths can be chosen for specific applications. Complexity analysis shows that the proposed architecture has the lowest latency and area complexity compared to related scalable architectures. Experimental results demonstrate that our design has area, speed, and flexibility advantages over related schemes.

关键词： algorithms implemented in hardware computations in finite fields computer arithmetic high-speed arithmetic VLSI

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On efficient implementation of FPGA-based hyperelliptic curve cryptosystems

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COMPUTERS & ELECTRICAL ENGINEERING 2007年第5-6期33卷 349-366页

作者： Elias, Grace Miri, Ali Yeap, Tet-Hin Univ Ottawa Sch Informat Technol & Engn Ottawa ON Canada

In this age, where new technological devices such as PDAs and mobile phones are becoming part of our daily lives, providing efficient implementations of suitable cryptographic algorithms for devices built on embedded systems is becoming increasingly important. This paper presents an efficient design of a high-performance hyperelliptic curve cryptosystem for a field programmable gate array which is well suited for embedded systems having limited resources such as memory, space and processing power. In this paper, we investigate two architectures, one using a projective coordinate representation for hyperelliptic systems and the second using a mixed coordinate representation that eliminates the need for field inversions in the point arithmetic, which has been proven to be expensive in both time and space. In addition, both architectures are based on an explicit formula which allows one to compute the point arithmetic directly in the finite field, thereby eliminating a level of arithmetic. The operation time for the HECC system is also improved by considering simplifications of the hyperelliptic curve which are accomplished through simple transformation of variables. As a result, these implementations offer significantly faster operation time and smaller area consumption then other HECC hardware implementations done to date. (C) 2007 Published by Elsevier Ltd.

关键词： reconfigurable hardware Public key cryptosystems algorithms implemented in hardware

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