This paper reports the design, proof-of-concept implementation and preliminary performance assessment of a lowcost, real-time, portable, low power, and small form factor GNSS rebroadcaster. This device can be used bot...
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ISBN:
(纸本)9781665416160
This paper reports the design, proof-of-concept implementation and preliminary performance assessment of a lowcost, real-time, portable, low power, and small form factor GNSS rebroadcaster. This device can be used both as a GNSS signal generator and as a GNSS signal regenerator. This device can be used to test the addition of new features in GNSS signals, such as new signals for ranging, and to characterize the performance of new and existing spoofing countermeasures for GNSS receivers in real time. This device does not require the use of post-processed GNSS signals, enabling the testing with live signals, for instance in a vehicular test campaign replicating the correct dynamic and channel impairments.
The detection of a person's eyes is a basic task in applications as important as iris recognition in biometric identification or fatigue detection in driving assistance systems. Current commercial and research sys...
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The detection of a person's eyes is a basic task in applications as important as iris recognition in biometric identification or fatigue detection in driving assistance systems. Current commercial and research systems use software frameworks that require a dedicated computer, whose power consumption, size and price are significantly large. This paper presents a hardware-based embedded solution for eye detection in real-time. From an algorithmic point-of-view, the popular Viola-Jones approach has been redesigned to enable highly parallel, single-pass image-processing implementation. Synthesized and implemented in an all-programmablesystem-on-chip (AP SoC), this proposal allows us to process more than 88 frames per second (fps), taking the classifier less than 2 ms per image. Experimental validation has been successfully addressed in an iris recognition system that works with walking subjects. In this case, the prototype module includes a CMOS digital imaging sensor providing 16 Mpixels images, and it outputs a stream of detected eyes as 640 x 480 images. Experiments for determining the accuracy of the proposed system in terms of eye detection are performed in the CASIA-Iris-distance V4 database. Significantly, they show that the accuracy in terms of eye detection is 100%.
This paper explores the idea of increasing attacker workload by hiding core operating system functions within Field programmable Gate Array (FPGA) logic, recently introduced within the fabric of high-performance embed...
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ISBN:
(纸本)9780769551241
This paper explores the idea of increasing attacker workload by hiding core operating system functions within Field programmable Gate Array (FPGA) logic, recently introduced within the fabric of high-performance embedded processors. The research is conducted in the context of a from-scratch microkernel operating system (BEAR [1]) under development at Dartmouth. This paper explains the performance costs and security enhancements associated with a rudimentary hardware scheduler on the Xilinx Zynq Z-7020 all programmable system-on-chip. Baseline measurements are collected for a traditional C-based software implementation. Implementations coded directly in VHDL and transformed from C to HDL via High Level Synthesis (HLS) are then compared. Performance and hardware resource utilization costs between AXI4 and AXI4-lite processor-FPGA interfaces are also evaluated.
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