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AI-Powered Revolution: Redefining analog circuit design and Optimization for Tomorrow

IEEE NANOTECHNOLOGY MAGAZINE 2025年第2期19卷 38-47页

作者： Kong, Zhi Hui James, Anusha Ata, Sezin Kircali Aung, Khin Mi Mi Foo, Chuan Sheng James, Ashish Yeo, Kiat Seng Singapore Univ Technol & Design SUTD Singapore 487372 Singapore ASTAR Inst Infocomm Res I2R Singapore 138632 Singapore ASTAR Ctr Frontier AI Res CFAR Singapore 138632 Singapore Tianjin Univ TJU Sch Microelect Tianjin 300072 Peoples R China Singapore Univ Technol & Design SUTD Engn Prod Dev Singapore 300072 Singapore

The infusion of Artificial Intelligence (AI) within the intricate realm of analog circuits presents a transformative opportunity. By seamlessly blending the precision of AI algorithms with the nuanced operation of analog components, the landscape of analog circuit design has undergone a revolutionary transformation, enabling dynamic adaptation, fine optimization, and intelligent assimilation of insights gleaned from past data. Nevertheless, analog circuits face stringent functional and technological constraints, leading to a scarcity of data for modelling, and additional data acquisition entails costly and time-consuming simulations. This article introduces novel methodologies designed to enhance simulation efficiency and reduce associated costs, thereby enabling efficient and effective AI-driven analog circuit design. By leveraging data-driven AI approaches, the focus is on exploration of promising and feasible circuit design regions, improving AI model accuracy, and substantially mitigating the reliance on extensive simulations and significant manual effort. The results demonstrate a marked advancement in analog circuit design, showcasing how data-centric AI approaches can refine the design process, making it more efficient and cost-effective. This work is poised to set the stage for future developments where analog circuit design can be conducted with greater precision and efficiency.

关键词： Artificial intelligence analog circuits circuit synthesis Data models Integrated circuit modeling Solid modeling Optimization Computational modeling Accuracy Supervised learning design methodology Active learning analog circuit design artificial intelligence bayesian optimization data-centric design automation initialization operational amplifier regression

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analog circuit design of Normalized Bistable Stochastic Resonance Model and Its Application in Weak Signal Processing

Analog Circuit Design of Normalized Bistable Stochastic Reso...

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International Conference on Networking and Network Applications (NaNA)

作者： Liu, Jin Li, Zan Miao, Qiguang Yang, Li Qi, Peihan Wang, Danyang Xidian Univ Sch Comp Sci & Technol Xian 710071 Peoples R China Xidian Univ State Key Lab Integrated Serv Networks Xian 710071 Peoples R China

ISBN: (纸本)9798350376784;9798350376777

The concept of stochastic resonance (SR) describes a counterintuitive phenomenon in which a weak signal can be enhanced by appropriate intensity of stochastic noise in a nonlinear bistable system, and it provides a new thought for weak signal processing. However, the classical SR theory has demonstrated that the resonance phenomenon occurs on condition that signal and noise obeying adiabatic approximation, i.e., signal with very low frequency and background gaussian white noise of variance less than one. Aiming at this, a normalized bistable stochastic resonance (NBSR) model can be built under adiabatic approximation condition. On this basis, using NBSR model as the reference model, SR technique can further be extended into practical weak signal processing in nonadiabatic approximation condition by linear conversion method. Considering key role of the NBSR model in building link between adiabatic approximation SR theory and it's expansion into practical application, an analog circuit design of NBSR model is studied, which provides a solution to signal oversampling problem in NBSR system digital realization. Furthermore, both numeric and circuit simulation experiments are given to validate the correctness of the NBSR system analog circuit design.

关键词： weak signal processing adiabatic approximation condition analog circuit design normalized bistable stochastic resonance (NBSR) signal oversampling

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InnovA: A Cognitive Architecture for Computational Innovation Through Robust Divergence and Its Application for analog circuit design

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IEEE TRANSACTIONS ON COMPUTER-AIDED design OF INTEGRATED circuitS AND SYSTEMS 2018年第10期37卷 1943-1956页

作者： Li, Hao Liu, Xiaowei Jiao, Uanshu Doboli, Alex Doboli, Simona SUNY Stony Brook Dept Elect & Comp Engn Stony Brook NY 11794 USA Hofstra Univ Dept Comp Sci Hempstead NY 11549 USA

This paper presents InnovA, a cognitive architecture for creative problem solving in analog circuit design, e.g., topology creation (synthesis), incremental topology modification, and design knowledge identification and reuse. The architectural modules attempt to replicate cognitive human activities, like concept formation, comparison, and concept combination. The architecture uses multiple knowledge representations organized using topological similarity and causality information. Solutions are clustered, so that each cluster represents a specific set of performance tradeoffs, thus a fragment of the Pareto front in the solution space. New structural features arc created through variation of existing features. New solutions are created by combining features from the same cluster, distinct clusters, and features that originate a new cluster. The related algorithms are discussed in this paper too. The architecture also incorporates modules mimicking the using of human emotions in memory formation and decision making, but these modules are still under development and are a main direction for our future work. This paper presents a number of examples to illustrate its using in various analog circuit design activities that are hard to be realized with traditional computational methods.

关键词： analog circuit design cognitive architecture constrained model robust divergence

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Incremental reinforcement learning for multi-objective analog circuit design acceleration

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ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE 2024年 129卷

作者： Abuelnasr, Ahmed Ragab, Ahmed Amer, Mostafa Gosselin, Benoit Savaria, Yvon Polytech Montreal Dept Elect Engn 2500 Chemin Polytech Montreal PQ H3T 1J4 Canada Laval Univ Dept Elect & Comp Engn 2325 Rue Univ Quebec City PQ G1V 0A6 Canada Polytech Montreal Dept Math & Ind Engn 2500 Chemin Polytech Montreal PQ H3T 1J4 Canada CanmetENERGY 1615 Lionel Boulet BlvdPOB 4800 Varennes PQ J3X 1P7 Canada Menoufia Univ Fac Elect Engn Menoufia 32952 Egypt

The design of high-performance analog circuits is a time-consuming process that requires the involvement of highly qualified designers and frequent tedious interactions with circuit simulators. This sets a need for a method that accelerates the circuit design process and reduces unnecessary designer -simulator interactions. Existing methods are either slow or unable to deal with complex tasks. This paper proposes a simulation -based optimization method based on a deep reinforcement learning (DRL) agent to optimize analog circuits and accelerate the design process. In this method, the DRL agent exploits the soft -actor -critic algorithm based on an improved reward function considering multiple conditions to expedite the parameters optimization step of analog circuits. The designer provides the RL agent with the circuit testbench, design requirements and circuit parameters. The agent then repetitively interacts with the circuit simulator to tune these parameters. In this work, an incremental RL approach is also proposed to deal with complex circuits. Incrementality is found to be increasingly beneficial as the circuit complexity increases (increased number of design parameters and competing objectives). The effectiveness of the proposed method was validated on a complex circuit defined by a design space comprising as many as 36 dimensions (17 design variables and 19 competing objectives). The reported results demonstrate that our method can significantly accelerate the design process and yield high-performance optimized designs. Notably, the required number of simulation steps is on the order of 1e3, which is one to two orders of magnitude more efficient than similar state-of-the-art DRL approaches.

关键词： analog circuit design Electronic circuit design Reinforcement learning Incremental learning Multi-objective optimization Simulation-based optimization

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FUNDAMENTALS OF LOW-NOISE analog circuit-design

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PROCEEDINGS OF THE IEEE 1994年第10期82卷 1515-1538页

作者： LEACH, WM Sch. of Electr. & Comput. Eng. Georgia Inst. of Technol. Atlanta GA

This paper presents a tutorial treatment of the fundamentals of noise in solid-state analog electronic circuits. It is written for upper division students and practicing engineers who wish to gain a basic knowledge of the theory of electronic noise and techniques for low-noise circuit design. The paper presents an overview of noise fundamentals, a description of noise models for passive devices and active solid-state devices, methods of calculating the noise performance of amplifiers, and techniques for minimizing noise in circuit design. The theory and methods are applicable to both discrete and integrated circuits.

关键词： active networks active solid-state devices amplifiers analog circuit design analogue circuits circuit design electronic noise low-noise analog circuit network synthesis noise models noise performance passive devices passive networks random noise solid-state analog electronic circuits thermal noise

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An evolutionary algorithm-based approach to robust analog circuit design using constrained multi-objective optimization

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KNOWLEDGE-BASED SYSTEMS 2008年第3期21卷 175-183页

作者： Nicosia, Giuseppe Rinaudo, Salvatore Sciacca, Eva Univ Catania Dept Math & Comp Sci I-95125 Catania Italy ST Microelect Catania Italy

The increasing complexity of circuit design needs to be managed with appropriate optimization algorithms and accurate statistical description of design models in order to reach the design specifics, guaranteeing "zero defects". In the design for Yield open problems are the design of effective optimization algorithms and statistical analysis for yield design, which require time consuming techniques. New methods have to balance accuracy, robustness and computational effort. Typical analog integrated circuit optimization problems are computationally hard and require the handling of multiple, conflicting, and non-commensurate objectives having strong nonlinear interdependence. This paper tackles the problem by evolutionary algorithms to produce tradeoff solutions on the Pareto Front. In this research work Integrated circuit (IC) design has been formulated as a constrained multi-objective optimization problem defined in a mixed integer/discrete/continuous domain. The following real-life circuits, RF Low Noise Amplifier, Leapfrog Filter, and Ultra Wideband LNA, were selected as test bed. The proposed algorithm, A-NSGAII, was shown to produce acceptable and robust solutions in the tested applications, where state-of-art algorithms and circuit designers failed. The results show significant improvement in all the chosen IC design problems. (c) 2008 Published by Elsevier B.V.

关键词： analog circuit design circuit sizing design for yield design for manufacturability genetic algorithms population-based algorithms evolutionary optimization multi-objective optimization constrained optimization

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Automated analog circuit design using two-layer genetic programming

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APPLIED MATHEMATICS AND COMPUTATION 2007年第2期185卷 1087-1097页

作者： Wang, Feng Li, Yuanxiang Li, Li Li, Kangshun Wuhan Univ Sch Comp Sci Wuhan 430072 Peoples R China Wuhan Univ State Key Lab Software Engn Wuhan 430072 Peoples R China Wuhan Univ Int Software Sch Wuhan 430072 Peoples R China Jiangxi Univ Sci & Technol Sch Informat Engn Jiangxi 341000 Peoples R China

analog circuits are very important in many high-speed applications such as communications. Since the size of analog circuit is becoming larger and more complex, the design is becoming more and more difficult. This paper proposes a two-layer evolutionary scheme based on genetic programming (GP), which uses a divide-and-conquer approach to evolve the analog circuits. Corresponding to the two-layer GP, a new representation of circuit has been proposed here and it is more helpful to generate expectant circuit graphs. This algorithm can evolve the circuits with dynamical size, circuit topology, and component values. The experimental results on the designs of the voltage amplifier and the low-pass filter show that this algorithm is efficient. (c) 2006 Elsevier Inc. All rights reserved.

关键词： evolutionary computation evolvable hardware genetic programming analog circuit design electrical circuits

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Chaos and Synchronization - Potential Ingredients of Innovation in analog circuit design?

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IEICE TRANSACTIONS ON ELECTRONICS 2024年第10期E107C卷 376-391页

作者： Minati, Ludovico Univ Elect Sci & Technol China Sch Life Sci & Technol Chengdu Peoples R China Tokyo Inst Technol Inst Innovat Res Yokohama 2268503 Japan

Recent years have seen a general resurgence of interest in analog signal processing and computing architectures. In addition, extensive theoretical and experimental literature on chaos and analog chaotic oscillators exists. One peculiarity of these circuits is the ability to generate, despite their structural simplicity, complex spatiotemporal patterns when several of them are brought towards synchronization via coupling mechanisms. While by no means a systematic survey, this paper provides a personal perspective on this area. After briefly covering design aspects and the synchronization phenomena that can arise, a selection of results exemplifying potential applications is presented, including in robot control, distributed sensing, reservoir computing, and data augmentation. Despite their interesting properties, the industrial applications of these circuits remain largely to be realized, seemingly due to a variety of technical and organizational factors including a paucity of design and optimization techniques. Some reflections are given regarding this situation, the potential relevance to discontinuous innovation in analog circuit design of chaotic oscillators taken both individually and as synchronized networks, and the factors holding back the transition to higher levels of technology readiness.

关键词： analog circuit design analog computing analog signal pro- cessing bio-inspired robots chaos chaos synchronization chaotic oscillator data augmentation distributed sensing force field hype cycle innovation neural systems pattern generation technology readiness

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Speciation-based genetic algorithm in analog circuit design

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TURKISH JOURNAL OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES 2016年第3期24卷 1022-1033页

作者： Karci, Hasari Tohumoglu, Gulay Nacaroglu, Arif Gaziantep Univ Dept Elect & Elect Engn Fac Engn Gaziantep Turkey Dokuz Eylul Univ Dept Elect & Elect Engn Fac Engn Tinaztepe Campus Izmir Turkey

This paper presents a speciation procedure that improves the local search capability of the genetic algorithm in analog circuit design. There is no need for additional circuit simulation in order to apply this procedure. The procedure is tested in Gaussian, sigmoid, cube, and square circuit design problems. Two sets of 125 simulations with the same seed values are performed for each problem using both the proposed procedure and the canonical genetic algorithm. The simulation results show that the method is statistically better than the canonical genetic algorithm, which suffers from bad locality. The effects of the population size and speciation threshold coefficient on the performance of the speciation algorithm are investigated. Confidence intervals of the simulation results are calculated. The results show that the speciation procedure improves the quality of solutions with at least 99% confidence, and the effectiveness of the method, which is statistically determined, increases in small populations.

关键词： Genetic algorithm genetic programming analog circuit design speciation local search

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Comparison of a BSIM3V3 and EKV MOSFET model for a 0.5 μm CMOS process and implications for analog circuit design

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2003年第4期50卷 915-920页

作者： Terry, SC Rochelle, JM Binkley, DM Blalock, BJ Foty, DP Bucher, M Univ Tennessee Knoxville TN 37996 USA Concorde Microsyst Inc Knoxville TN 37996 USA Univ N Carolina Charlotte NC 28223 USA Gilgamesh Associates Fletcher VT 05444 USA Natl Tech Univ Athens GR-15773 Athens Greece

design requirements for high-density detector front-ends and other high-performance analog systems routinely force designers to operate devices in moderate inversion. However, CMOS models have traditionally not handled this operating region very well. In this paper, the Berkeley Short-Channel IFGET Model (BSIM3V3) and EKV 2.6 MOSFET models are evaluated in terms of their ability to model low-voltage analog circuits. Simulation results for a standard 0.5 mum. CMOS process are presented and compared to measured data. The data presented includes simulated and measured output conductance and transconductance efficiency for devices with channel lengths ranging from 0.5 mum. to 33 mum. In addition, the models are compared in terms of their ability to handle the different operating regions of the MOS transistor (weak, moderate, and strong inversion). The results highlight the difficulty of obtaining a model that accurately predicts the operation of high-performance analog systems.

关键词： analog circuit design BSIM3V3 CMOS modeling EKV 2.6 inversion coefficient transconductnce efficiency

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