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A CMOS Hard-Decision analog Convolutional decoder Employing the MFDA for Low-Power Applications

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2008年第9期55卷 2912-2923页

作者： Tomatsopoulos, Billy Demosthenous, Andreas UCL Dept Elect & Elect Engn London WC1E 7JE England

The use of analog circuits to reduce the size and power consumption of channel decoders such as Viterbi decoders has been an active area of research over the recent years. However, the need for digital memory to store the history of the path elimination decisions in a Viterbi decoder, limits the potential advantages that could be offered by an all-analog convolutional decoder implementation. This is especially so in cases where the use of an older silicon process technology is dictated by the application;hence, the power-reduction benefits offered by deep sub-micrometer digital designs cannot be exploited. A novel alternative convolutional decoding method which allows for an entirely analog implementation is the modified feedback decoding algorithm (MFDA). This paper describes the first integrated realization of a convolutional decoder employing the MFDA. The rate-1/2, constraint-length-3 decoder, employs a current-mode analog signal processing core and was fabricated in a 0.6-mu m CMOS process technology, occupying an area of 0.5 mm(2). Measured results show that decoding speeds in excess of 1-Mb/s are possible with virtually no loss in coding gain. Total power consumption is 2.45 mW from a single 3-V supply. Although a hard-decision decoder, conversion to soft-decision decoding requires only the inclusion of a simple analog delay line as shown in the paper. The decoder is dedicated to an implantable biotelemetry system, but it can also find use in other low-power applications. System-level coding simulations are also presented which are useful for the construction of larger decoders where the benefits of the MFDA approach would be more pronounced.

关键词： analog decoder convolutional codes current-mode circuits implanted devices modified feedback decoding algorithm (MFDA) telemetry Viterbi decoder

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The decoder of trellis code implemented by CMOS analog circuits

The decoder of trellis code implemented by CMOS analog circu...

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7th International Conference on ASIC

作者： Yang, Shuhui Li, Denghua Qiu, Yulin Beijing Informat S&T Univ Dept Info & Comm Beijing 100101 Peoples R China Chinese Acad Sci Inst Microelect Beijing 100029 Peoples R China

ISBN: (纸本)9781424411313

This paper analyses some circuits of the analog decoder of (5,2,3) trellis code, which is implemented by CMOS analog circuits. The decoding performance of the analog decoder is given. Simulation results show that the analog decoder decreases at least one decimal power consumption and chip area at the same bit rate, compared with the digital decoder. For the Turbo code and LDPC, if they are decoded by digital circuits, the quantity of the transistors and the computing power will be very great. If we use analog decoder, the power consumption and the chip area will be very small.

关键词： analog decoder trellis-code probability decoding turbo code CMOS

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Study on a new-style probability decoder implemented by analog LSI 5

Study on a new-style probability decoder implemented by anal...

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5th International Conference on ASIC

作者： Yang, SH Qiu, YL CAS Ctr Microelect Beijing 100029 Peoples R China

ISBN: (纸本)078037889X

In this paper we design an analog multiplier by the MOS transistors working in the subthreshold mode. Using the multiplier as the core circuit, we design a famly of modules which can compute the probability by the current. On the basis of these modules, the pipelining serial-to-parallel interface, and the maximum a posteriori probability (MAP) algorithm, we implement a novel soft-decision analog probability decoder of the (5,2,3) trellis code. With the standard 0.6 mum CMOS technology we simulate and verify the analog decoder.

关键词： multiplier MAP soft-decision decoding trellis code analog decoder

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analog Integrated Circuit Design of a Hypertrellis decoder

Analog Integrated Circuit Design of a Hypertrellis Decoder

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The Fourth International Conference on Parallel and Distributed Computing, Applications and Technologies

作者： Zong-Qi Hu Wai Ho Mow Wing-Hung Ki Department of Electrical and Electronic Engineering The Hong Kong University of Science and Technology Clear Water Bay Hong Kong SARChina

The first integrated analog hypertrellis decoder for a non-binary(5,4) single check code over Z4(the integer ring modulo 4) is *** is performed at 50MHz in cascode current mode for efficient routing,accuracy and *** decision outputs are generated for efficient testing,while soft outputs are available for accuracy *** chip is designed in a 0.5μm Agilent CMOS n-well process and occupies an area of 3.8 mm.

关键词： Hypertrellis Current Mode analog decoder

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analog Integrated Circuit Design of a Hypertrellis decoder

Analog Integrated Circuit Design of a Hypertrellis Decoder

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Proceedings of The Fourth International Conference on Parallel and Distribyted Computing,Applications and Technologies(第四届并行与分布式计算应用与技术国际会议)

作者： Zong-Qi Hu Wai Ho Mow Wing-Hung Ki Department of Electrical and Electronic Engineering The Hong Kong University of Science and Technology Clear Water Bay Hong Kong SAR China

ISBN: (纸本)0780378407

The first integrated analog hypertrellis decoder for a non-binary (5, 4) single check code over Z4 (the integer ring modulo 4) is presented. Computation is performed at 50MHz in cascode current mode for efficient routing, accuracy and speed. Hard decision outputs are generated for efficient testing, while soft outputs are available for accuracy testing. The chip is designed in a 0.5μm Agilent CMOS n-well process and occupies an area of 3.8 mm2.

关键词： Hypertrellis Current Mode analog decoder

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Density evolution analysis of device mismatch in analog decoders

Density evolution analysis of device mismatch in analog deco...

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IEEE International Symposium on Information Theory

作者： Winstead, C Schlegel, C Univ Alberta iCORE HCDC Ltd Edmonton AB T6G 2V4 Canada

ISBN: (纸本)0780382803

All analog circuits are affected by device mismatch, slight errors in the physical characteristics of analog devices. In many applications, mismatch reduces precision, making power and complexity advantages irrelevant. In this paper, we examine the effects of mismatch for decoders based on Gilbert multipliers and the sum-product algorithm.

关键词： analogue circuits iterative decoding parity check codes analog decoder device mismatch Gilbert multiplier sum-product algorithm density evolution analysis

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A 25MHz Sign and Magnitude Converter for analog Current Mode Iterative decoders

A 25MHz Sign and Magnitude Converter for Analog Current Mode...

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IEEE Asia Pacific Conference on Circuit and System (APCCAS)

作者： Lo, Ming-Yam Ki, Wing-Hung Mow, Wai-Ho Hong Kong Univ Sci & Technol Dept Elect & Comp Engn Clear Water Bay Hong Kong Peoples R China

A 25MHz low-power sign and magnitude (SAM) converter for processing bi-directional currents is proposed. It converts the lowest current of +/- 1 mu A in less than 40ns, and does not require any static bias currents. T... 详细信息

ISBN: (纸本)9781424474561

关键词： analog decoder current mode iterative decoder magnitude sign

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A 25MHz Sign and Magnitude Converter for analog Current Mode Iterative decoders

A 25MHz Sign and Magnitude Converter for Analog Current Mode...

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IEEE Asia Pacific Conference on Circuits and Systems

作者： Ming-Yam Lo Wing-Hung Ki Wai-Ho Mow Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology

A 25MHz low-power sign and magnitude (SAM) converter for processing bi-directional currents is proposed It converts the lowest current of ±1μA in less than 40ns, and does not require any static bias currents. Th... 详细信息

ISBN: (纸本)9781424474547

关键词： analog decoder Current mode Iterative decoder Magnitude Sign

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