analog in memory computing (IMC) has emerged as a promising method to accelerate deep neural networks (DNNs) on hardware efficiently. Yet, analog computation typically focuses on the multiply and accumulate operation,...
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ISBN:
(纸本)9798350383638;9798350383645
analog in memory computing (IMC) has emerged as a promising method to accelerate deep neural networks (DNNs) on hardware efficiently. Yet, analog computation typically focuses on the multiply and accumulate operation, while other operations are still being computed digitally. Hence, these mixed-signal IMC cores require extensive use of data converters, which can take a third of the total energy and area consumption. Alternatively, all-analog DNN computation is possible but requires increasingly challenging analog storage solutions, due to noise and leakage of advanced technologies. To enable all-analog DNN acceleration, this work demonstrates a feasible IMC architecture using an efficient analog main memory (AMM) cell. The proposed AMM cell is 42x and 5x more power and area efficient than a baseline analog storage cell. An all-analog architecture using this cell achieves potential efficiency gains of 15x compared with a mixed-signal IMC core using data converters.
The memristor-based array architecture promises an efficient analog implementation of the multiply -add engine that can have significant impact in signal processing and neural network implementations. The ability to r...
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ISBN:
(纸本)9781538681671
The memristor-based array architecture promises an efficient analog implementation of the multiply -add engine that can have significant impact in signal processing and neural network implementations. The ability to represent a negative conductance value to correspond to a negative matrix element is one of the main challenges associated with analog memristor array implementation. In this paper, a re -configurable general purpose single array architecture is proposed to realize a multiply -add operation that allows both positive and negative conductance values. The architecture utilizes memristor devices with two different characteristics, one for computation and one for storage. The proposed design has been verified using LTSpice circuit simulator. Several cases with different combinations of polarities for the input voltage and conductance values were demonstrated.
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