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analog processing circuits for a 1.1 V 270 /spl mu/A mixed-signal hearing aid chip

IEEE International Conference on Solid-State circuits (ISSCC)

作者： J.W. Fattaruso J.R. Hochschild W. Sjursen Lieyi Fang D.G. Gata C.M. Branch J. Holmes Zhongnong Jiang Shuyou Chen Kuok Ling E. Petilli M.L. Skorcz R.R. Dickerson W.A. Severin Texas Instruments Inc. Dallas TX USA Songbird Hearing Cranbury NJ USA Intrinsix Corporation Rochester NY USA

A compressing preamplifier, ADC, DAC, output driver and clock oscillator are implemented in a mixed-signal BiCMOS hearing-aid chip with digital filtering. 2.8 /spl mu/V input noise floor over the audio band and 0.02 %... 详细信息

ISBN: (纸本)0780373359

关键词： analog processing circuits Preamplifiers Driver circuits Clocks Oscillators BiCMOS integrated circuits Digital filters Filtering Circuit noise Batteries

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Design and Testing of a 0.8-V Low-Voltage High-Rate Prototype Readout ASIC for the Micro-Pattern Gas Detector

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2025年第3期72卷 668-677页

作者： Li, Jiaming Qin, Jiajun Yang, Ziyu Yang, Xincheng Cao, Zhe Zhao, Lei Univ Sci & Technol China State Key Lab Particle Detect & Elect Hefei 230026 Peoples R China Univ Sci & Technol China Dept Modern Phys Hefei 230026 Peoples R China

The micro-pattern gas detectors (MPGDs) offer high spatial and time resolution and a large active area, among which the micro-resistive WELL ( mu RWELL) detector has received increasing attention in recent years due to its simple structure, low material budget, and high counting rate capability. It is, therefore, proposed as an important option for the low-mass Inner TracKer (ITK) detector in the future Super Tau-Charm Facility (STCF). Considering the high luminosity in the STCF, the innermost ITK layer requires a new high-rate, low-noise, and low-power readout application-specific integrated circuit (ASIC). The first version of the prototype ASIC integrates a 32-channel analog processing circuit. In the charge-sensitive amplifier (CSA), the bulk-driven current mirror is adopted to reduce the headroom voltage and lower the supply voltage to 0.8 V, thereby reducing power consumption while maintaining the same channel thermal noise and transconductance. In addition, an equivalent "cold resistor" circuit is proposed to achieve both fast recovery and low noise. This ASIC has been fabricated in a 0.18- mu m CMOS process, and a series of tests has been performed. The equivalent noise charge (ENC) is measured to be 487 e(- )+ 29.2 e(-) /pF with a charge measurement range of 40 fC and a peaking time of 25 ns. Meanwhile, the maximum repetition rate capability per channel at a 70-ns charge collection time is up to 4 MHz, while the power consumption is only 1.93 mW per channel, resulting in a figure of merit (FOM) of only 0.29 pJ.

关键词： Noise Detectors Prototypes Spatial resolution Low voltage Current mirrors Charge measurement Application specific integrated circuits analog processing circuits Transconductance Application-specific integrated circuit (ASIC) front-end electronics low-voltage micro-pattern gas detector (MPGD) micro-resistive WELL (mu RWELL)

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Inverse Design of Multi-Input Multi-Output 2-D Metastructured Devices

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IEEE TRANSACTIONS ON ANTENNAS AND PROPAGATION 2022年第5期70卷 3495-3505页

作者： Szymanski, Luke Gok, Gurkan Grbic, Anthony Univ Michigan Dept Elect Engn & Comp Sci Radiat Lab Ann Arbor MI 48109 USA Raytheon Technol Res Ctr E Hartford CT 06108 USA

In this work, an optimization-based inverse-design method is provided for multi-input-multioutput (MIMO) metastructured devices. Typically, optimization-based methods use a full-wave solver in conjunction with an optimization routine to design devices. Due to the computational cost, this approach is not practical for designing electrically large aperiodic metastructured devices. To address this issue, a 2-D circuit network solver using reduced-order models of the metastructure's unit cells is introduced. The circuit network solver is used in conjunction with a gradient-based optimization routine that uses the adjoint variable method to solve large-scale optimization problems such as those posed by metastructured devices. To validate the inverse-design method, a planar beamformer and an analog signal processor for aperture field reconstruction are designed and validated with full-wave simulations.

关键词： Voltage Optimization MIMO communication Mathematical models Performance evaluation Computational efficiency Reduced order systems analog processing circuits antenna radiation pattern synthesis metastructures microwave circuits optimization methods

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Single ping - Multiple measurements: Sonar bearing angle estimation using spatiotemporal frequency filters

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IEEE TRANSACTIONS ON circuits AND SYSTEMS I-REGULAR PAPERS 2006年第4期53卷 769-783页

作者： Clapp, MA Etienne-Cummings, R Johns Hopkins Univ Dept Elect & Comp Engn Baltimore MD 21218 USA

Presented is a mixed-signal full-custom VLSI chip designed to receive sonar return signals from an ultrasonic microphone array, and extract input bearing angles of the incoming signals. processing utilizes simple low-power analog spatiotemporal bandpass filters to extract wavefront velocity across the array, which translates to input bearing angle. processing uses phase information of array signals, not onset or offset of ultrasonic burst. With such synchronous processing, multiple angle readings from different returns of the same ultrasonic transmit burst are possible. Compatible microphone arrays are compact in size-test array has a total baseline of 26.5 mm. In a test with ultrasonic beacon 65 cm from a microphone array, angular precision of 1 degrees was demonstrated in most instances in the range -60 degrees to 60 degrees. Applications include sonar localization of remote objects, sonar imaging, and improved interference rejection between objects within the field of view of the sensor microphones. The chip was fabricated on a standard 3M2P CMOS process with a 0.5-mu m feature size.

关键词： acoustic arrays acoustic beam steering acoustic imaging acoustic signal analysis analog processing circuits array signal processing bandpass filters continuous-time systems frequency-domain analysis intelligent sensors linear arrays mobile robot motion-planning object detection phased arrays robot sensing systems sensor processing signal processing sonar arrays sonar imaging sonar signal processing spatial filters spatiotemporal filters synchronous detection time-frequency analysis

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A CMOS transceiver for 10-Mb/s and 100-Mb/s Ethernet

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IEEE JOURNAL OF SOLID-STATE circuits 1998年第12期33卷 2169-2177页

作者： Everitt, J Parker, JF Hurst, P Nack, D Konda, KR Level One Commun Sacramento CA 95827 USA Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

A CMOS IC that implements the 802.3 Ethernet standards for 10- and 100-Mb/s data rates is described. The circuit uses mixed-signal techniques to perform transmit pulse shaping, receive adaptive line equalization, baseline wander compensation, and timing recovery. The IC occupies 23 mm(2) in a 0.6-mu m single-poly CMOS process and dissipates 850 mW from a 5-V supply.

关键词： analog processing circuits data communication local-area networks mixed analog-digital integrated circuits

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Versatile precision full-wave rectifiers for instrumentation and measurements

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2007年第5期56卷 1703-1710页

作者： Gift, Stephan J. G. Maundy, Brent Univ W Indies Dept Elect & Comp Engn St Augustine Trinidad Tobago Univ Calgary Dept Elect & Comp Engn Calgary AB T2N 1N4 Canada Assoc Profess Engineers Trinidad & Tobago St Augustine Trinidad Tobago

This paper analyzes the performance of a family of high-quality precision full-wave rectifiers that utilize operational conveyors. The circuits have high precision, wide bandwidth, and high accuracy and are superior to the corresponding operational-amplifier (op amp)-based circuits. Using the LF351 op amp, they are able to rectify signals up to 100 kHz and beyond with little or no distortion. PSPICE results for the circuits are presented.

关键词： analog processing circuits current conveyors instrumentation operational amplifiers (op amps) rectifiers

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analog Multiply-Accumulate Cell With Multi-Bit Resolution for All-analog AI Inference Accelerators

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IEEE TRANSACTIONS ON circuits AND SYSTEMS I-REGULAR PAPERS 2023年第9期70卷 3509-3521页

作者： Nagele, Raphael Finkbeiner, Jakob Stadtlander, Valentin Grozing, Markus Berroth, Manfred Univ Stuttgart Inst Elect & Opt Commun Engn D-70569 Stuttgart Germany Tech Univ Dresden Chair Circuit Design & Network Theory D-01069 Dresden Germany

Mixed-signal AI accelerators offer the possibility of higher energy efficiency for moderate resolution computations compared to their digital counterparts. All-analog implementations, where all operations are performed in the analog domain, can further improve this energy advantage. An energy efficient multiply-accumulate cell for all-analog neural layer processing macros is presented. The proposed analog two-quadrant multiplier circuit consists of two complementary MOSFETs where the pulse width modulated input activation is applied to the gates and the weight signal to the isolated back-gate. The analog multi-bit resolution weight is dynamically stored on a memory capacitor. The multiply-accumulate operation result is represented by charge accumulated on a summation line and drawn from or put onto a computation capacitance. Simulation results based on a 22 nm FD-SOI CMOS technology show that the cell consumes about 0.67 fJ for a circuit-level multiply-accumulate operation. An area efficiency of 166 x 10(12) MAC/s/mm(2) is achieved.

关键词： analog integrated circuits analog processing circuits multiplying circuits neural network hardware AI accelerators

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analog VLSI implementation of the help if needed stereopsis algorithm

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IEEE TRANSACTIONS ON circuits AND SYSTEMS II-analog AND DIGITAL SIGNAL processing 2000年第11期47卷 1328-1337页

作者： Titus, AH Drabik, TJ Rochester Inst Technol Dept Elect Engn Rochester NY 14623 USA

This brief introduces a novel clocked analog VI,SI hardware system with an optical input that performs stereopsis. An algorithm called the Help If Needed Algorithm, developed previously, is readily mapped unto an analog VLSI platform. The system fits into the cellular neural network (CNN) paradigm. The circuit components that make up the cells of the CNN are designed with the constraint that they must function effectively and fit into the space available. In order to clarify the processing pathway, the system is described at the component and system levels. Each cell has an optical input, while the output is electrical. By utilizing an optical input, an analog VLSI silicon retina first stage can be connected to the stereopsis processor completely in parallel, creating a multi-stage artificial visual system. The physical system is composed of 2.0 mum Tinychips fabricated through MOSIS. Experimental data are presented that verify that the system performs as desired and successfully implements the Help If Needed Stereopsis Algorithm. The novel stereopsis processor is ideally suited for autonomous robots. or any application that requires a low power visual processing system.

关键词： analog processing circuits CMOS analog integrated circuits machine vision neural network hardware very large scale integration

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Template design for cellular nonlinear networks with 1-bit weights

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IEEE TRANSACTIONS ON circuits AND SYSTEMS I-REGULAR PAPERS 2008年第3期55卷 904-913页

作者： Laiho, Mika Paasio, Ari Flak, Jacek Halonen, Kari A. I. Univ Turku Microelect Lab FIN-20520 Turku Finland Aalto Univ Espoo 02015 Finland Univ Turku Microelect Lab FIN-20520 Turku Finland Aalto Univ Elect Circuit Design Lab FIN-02150 Espoo Finland VTT Tech Res Ctr Espoo 02044 Finland Aalto Univ Elect Circuit Design Lab FIN-02150 Espoo Finland

In this paper, we show how a cellular nonlinear network with 1-bit weight programmability can be used for processing black and white image data. When using such a binary-programmable network, some templates need to be processed algorithinically, in other words, divided into subtasks that are processed consecutively. We classify templates into groups based on their properties and give guidelines as to how the division into subtasks (when applicable) is performed. A large collection of templates suitable for the proposed model is shown. We also describe one possible cell structure that realizes the binary-programmable model. The cell is modeled with Matlab and selected template simulations are shown.

关键词： analog processing circuits cellular neural networks (CNNs) image processing parallel architectures threshold logic

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An 8 x 8 Cell analog Order-Statistic-Filter Array With Asynchronous Grayscale Morphology in 0.13-μm CMOS

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IEEE TRANSACTIONS ON circuits AND SYSTEMS I-REGULAR PAPERS 2009年第8期56卷 1541-1553页

作者： Poikonen, Jonne Paasio, Ari Univ Turku Dept Informat Technol Turku 20014 Finland

This paper presents an integrated 8 x 8 cell image processor array demonstrating the parallel implementation of analog order-statistic filtering and grayscale mathematical morphology. Each cell, connected locally to four nearest neighbors and sized 30 x 28 mu m(2), includes a digitally programmable five-input analog current-mode ranked-order filter. The array also demonstrates an implementation of asynchronously propagating morphological grayscale reconstruction, which is robust against device mismatch. The measurement results of all programmable order-statistic operations are shown, verifying the correct operation of the array. The chip was manufactured in a 0.13-mu m 1-poly 6-metal CMOS technology and operates from a single 1.3-V power supply.

关键词： analog processing circuits cellular arrays image processing image segmentation nonlinear filters order-statistic filtering ranked-order (RO) filters

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