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International Conference on Computational Techniques in Information and Communication Technologies (ICCTICT)

作者： Arora, Tajinder Singh Sharma, R. K. Maharaja Surajmal Inst Technol Dept Elect & Communcat Engn New Delhi India Ambedkar Inst Adv Commun Technol & Res Dept Elect & Communcat Engn Delhi India

ISBN: (纸本)9781509000821

This paper proposes a KHN equivalent biquad using third generation current conveyor (CCIII). The proposed current mode filter circuit is derived from the adjoint signal flow graph corresponding to the classical KHN filter. The proposed multi-input and single-output biquad offers all the advantages of KHN biquad. The derived circuit can realize all the five responses (Low pass, High Pass, Band pass, All pass and Band stop) without the need of any additional active/passive component. To validate the circuit workability software simulations have been done using PSPICE. Non-ideal analysis and sensitivity analysis of the filter circuit is also shown in this paper.

关键词： Active Filters analog processing circuits Biquadratic Filters Biquadratic Functions Current conveyors

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LOW-POWER analog SMART CAMERA SENSOR FOR EDGE DETECTION 23

LOW-POWER ANALOG SMART CAMERA SENSOR FOR EDGE DETECTION

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23rd IEEE International Conference on Image processing (ICIP)

作者： Soell, C. Shi, L. Roeber, J. Reichenbach, M. Weigel, R. Hagelauer, A. FAU Inst Elect Engn Erlangen Germany FAU Chair Comp Architecture Erlangen Germany

ISBN: (纸本)9781467399616

This work presents an intelligent analog image sensor system for smart camera applications with the need of edge or marker detection. The system consists of a 3x3 read-out CMOS image sensor, an analog Sobel stage and additional circuitry like operational amplifiers and comparators to compute a 1bit image with the edges present in the taken photo. This information can then be further processed digitally to detect specific shapes in order to control robot routines, for example. The architecture of the proposed system is highly desirable as dedicated analog hardware has significant advantages in terms of power and speed compared to digital implementations. The overall system is simulated with the help of a 3x3 CMOS image sensor IC as well as Cadence Virtuoso for analog circuit simulation and MATLAB to convert the sequential information back to an image, and compared to other state of the art CMOS image sensors with edge detection capability. The analog Sobel circuit runs with a clock of 10 MHz and consumes less than 0.79 mW average power for the computation of the example image, and the whole 200x200 pixel image sensor consumes only 5.5 mW at a frame rate of 75 fps.

关键词： Smart Camera CMOS Image Sensor analog processing circuits analog Sobel GRK-1773

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An Integrate-and-Dump Receiver for High Dynamic Range Photonic analog-to-Digital Conversion

An Integrate-and-Dump Receiver for High Dynamic Range Photon...

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IEEE 12th Topical Meeting on Silicon Monolithic Integrated circuits in RF Systems (SiRF)/Radio and Wireless Week (RWW)

作者： Gathman, Timothy D. Buckwalter, James F. Univ Calif San Diego Dept ECE La Jolla CA 92093 USA

ISBN: (纸本)9781457713163

A high-linearity integrate-and-dump circuit is proposed for the electrical interface to a photonic sampling system. The integrate-and-dump receiver operates at 2 GS/s with a 500ps period for integration, hold, and reset. Better than 7.5 ENOB is measured with a sinewave input. The integrate-and-dump receiver is fabricated in a 120nm SiGe BiCMOS technology with a core current consumption of 84 mA from a 5 V supply.

关键词： analog-digital conversion analog processing circuits signal sampling timing jitter

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Design of Main Board for ATLAS TileCal Demonstrator 19

Design of Main Board for ATLAS TileCal Demonstrator

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19th IEEE-NPSS Real Time Conference (RT)

作者： Tang, F. Akerstedt, H. Anderson, K. Bohm, C. Hildebrand, K. Muschter, S. Oreglia, M. Univ Chicago Enrico Fermi Inst 5640 S Ellis Ave Chicago IL 60637 USA Stockholm Univ Stockholm Sweden

ISBN: (纸本)9781479936595

The TileCal Demonstrator is a prototype for a future upgrade to the ATLAS hadron calorimeter when the Large Hadron Collider increases its luminosity in year 2023 (HL-LHC). It will be used for functionality and performance tests. The Demonstrator has 48 channels of upgraded readout and digitizing electronics and a new digital trigger capability, but stays backwards compatible with the present detector system by providing analog trigger signals. The Demonstrator is comprised of 4 identical "mini-drawers", each equipped with up to 12 photomultipliers (PMTs). The on-detector electronics includes 45 Front-End Boards, each serving an individual PMT;4 Main Boards, each to control and digitize the 12 PMT signals, and 4 corresponding high-speed Daughter Boards serving as data hubs between on-detector and off-detector electronics. The Demonstrator is fully compatible with the present system, accepting ATLAS triggers, timing and slow control commands for the data acquisition, detector control, and detector operation monitoring. We plan to insert one fully functional Demonstrator module into the present ATLAS TileCal detector for the LHC RUN 2 in August 2014. This paper will only cover the design of the Main Board.

关键词： analog processing circuits Circuit noise Pulse measurements analog-digital conversion Tile Calorimeter

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Low-power analog Lock-In Amplifier for High-resolution Portable Sensing Systems

Low-power Analog Lock-In Amplifier for High-resolution Porta...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Maya-Hernandez, P. M. Sanz-Pascual, M. T. Calvo, B. Inst Nacl Astrofis Opt & Electr Dept Elect Tonantzintla Puebla Mexico Univ Zaragoza Grp Elect Design I3A Zaragoza Spain

ISBN: (纸本)9781479953417

This paper presents the design of an analog lock-in amplifier (LIA) using a 0.18 mu m CMOS process with a single supply voltage of 1.8V. Targeting high-resolution portable sensing applications, the circuit has been optimized in terms of power consumption (928 mu W) and size (0.045mm(2) silicon area), while exhibiting high gain (98dB) with very low input-referred noise (<19.8nV/Hz(1/2) in the range 20kHz-950kHz). Post-layout simulation results demonstrate a resolution of 200nV and a dynamic reserve of 46.5 dB.

关键词： analog processing circuits lock-in amplifiers low-voltage low-power programmable circuits

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Towards analog Neural Networks Integrated in Detectors Readout 54th

Towards Analog Neural Networks Integrated in Detectors Reado...

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54th Meeting of the Italian Electronics Society

作者： Di Giacomo, Susanna Ronchi, Michele Carminati, Marco Fiorini, Carlo Politecn Milan Dipartimento Elettron Informaz & Bioingn Milan Italy Ist Nazl Fis Nazl Sez Milano Milan Italy

ISBN: (纸本)9783031487132;9783031487118;9783031487101

The conceptual design of a novel ASIC in 0.35 mu m CMOS technology implementing in an analog way an artificial neural network (ANN) with 64 inputs, 2 20-neuron hidden layers and 2 outputs is presented. The ANN was optimized to address the application in medical imaging based on emission tomography, in particular the estimation of the position of absorption of a gamma-ray photon in a crystal scintillator readout by a planar array of silicon photomultipliers. The key advantage of this analog approach, as opposed to digital ones, is the possibility of integrating local processing with the detector front-end and, thus, significantly reduce the number of signals (from 64 to 2) that have to be transmitted and digitized. This would allow an easier scale up of scanners for molecular imaging and diagnostics with larger fields of view, i.e. larger amount of imaging modules and/or pixels per module. However, given the widespread use of ANNs in a broad variety of sensing contexts, we believe that such as concept could be extended to several applications beyond gamma cameras.

关键词： analog processing circuits Radiation detectors In-memory computing Embedded machine learning In-sensor processing

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An 8 x 8 Cell analog Order-Statistic-Filter Array With Asynchronous Grayscale Morphology in 0.13-μm CMOS

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IEEE TRANSACTIONS ON circuits AND SYSTEMS I-REGULAR PAPERS 2009年第8期56卷 1541-1553页

作者： Poikonen, Jonne Paasio, Ari Univ Turku Dept Informat Technol Turku 20014 Finland

This paper presents an integrated 8 x 8 cell image processor array demonstrating the parallel implementation of analog order-statistic filtering and grayscale mathematical morphology. Each cell, connected locally to four nearest neighbors and sized 30 x 28 mu m(2), includes a digitally programmable five-input analog current-mode ranked-order filter. The array also demonstrates an implementation of asynchronously propagating morphological grayscale reconstruction, which is robust against device mismatch. The measurement results of all programmable order-statistic operations are shown, verifying the correct operation of the array. The chip was manufactured in a 0.13-mu m 1-poly 6-metal CMOS technology and operates from a single 1.3-V power supply.

关键词： analog processing circuits cellular arrays image processing image segmentation nonlinear filters order-statistic filtering ranked-order (RO) filters

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Optical and Electrical Memories for analog Optical Computing

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IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS 2023年第2期29卷

作者： Kari, Sadra Rahimi Ocampo, Carlos A. Rios A. Jiang, Lei Meng, Jiawei Peserico, Nicola Sorger, Volker J. J. Hu, Juejun Youngblood, Nathan Univ Pittsburgh Swanson Sch Engn Dept Elect & Comp Engn Pittsburgh PA 15261 USA Univ Maryland Dept Mat Sci College Pk MD 20742 USA Univ Maryland Inst Res Elect & Appl Phys College Pk MD 20742 USA Indiana Univ Bloomington Dept Intelligent Syst Engn Bloomington IN 47408 USA George Washington Univ Sch Engn & Appl Sci Dept Elect & Comp Engn Washington DC 20052 USA Optelligence LLC Upper Marlboro MD 20772 USA MIT Dept Mat Sci & Engn Cambridge MA 02139 USA

Key to recent successes in the field of artificial intelligence (AI) has been the ability to train a growing number of parameters which form fixed connectivity matrices between layers of nonlinear nodes. This "deep learning " approach to AI has historically required an exponential growth in processing power which far exceeds the growth in computational throughput of digital hardware as well as trends in processing efficiency. New computing paradigms are therefore required to enable efficient processing of information while drastically improving computational throughput. Emerging strategies for analog computing in the photonic domain have the potential to drastically reduce latency but require the ability to modify optical processing elements according to the learned parameters of the neural network. In this point-of-view article, we provide a forward-looking perspective on both optical and electrical memories coupled to integrated photonic hardware in the context of AI. We also show that for programmed memories, the READ energy-latency-product of photonic random-access memory (PRAM) can be orders of magnitude lower compared to electronic SRAMs. Our intent is to outline path for PRAMs to become an integral part of future foundry processes and give these promising devices relevance for emerging AI hardware.

关键词： Optical computing Memory management Photonics Ultrafast optics Optical noise Computer architecture Optical crosstalk Artificial intelligence neural network hardware analog computers optical computing analog processing circuits

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An Externally Linear-Internally Nonlinear RMS-to-DC Converter

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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT 2021年 70卷

作者： Pilsniak, Adam Kampik, Marian Silesian Tech Univ Dept Measurement Sci Elect & Control PL-44100 Gliwice Poland

The article presents a root mean square (RMS) to direct current (dc) converter based on an externally linear-internally nonlinear (ELIN) filter. The converter contains an averaging filter and two nonlinear blocks. The principle of operation of an ELIN circuit using an example of the ELIN integrator was presented. Three converters were developed and simulated each using four multiplier/divider integrated circuits. Preliminary tests of the input dynamic range of the three circuits were made by SPICE simulations. The prototype of the RMS-todc converter with a third-degree ELIN filter shows an improved dynamic range in comparison to classic "implicit square-rooting" converters as its error is reduced at lower amplitudes of the input voltage. The measured bandwidth of the ELIN converter prototype is wider in comparison to the "implicit square-rooting" converter prototype, built from nominally the same nonlinear components. The converter based on the presented circuit can be used in applications, where a wide voltage range and wide bandwidth are needed.

关键词： AC voltage analog processing circuits externally linear-internally nonlinear (ELIN) filters multiplying circuits nonlinear circuits root mean square (RMS)

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Minimal configuration precision full-wave rectifier using current and voltage conveyors

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IEICE ELECTRONICS EXPRESS 2010年第12期7卷 844-849页

作者： Koton, Jaroslav Herencsar, Norbert Vrba, Kamil Brno Univ Technol Dept Telecommun Brno 61200 Czech Republic

In this paper, new minimal configuration precision full-wave rectifier is presented. The structure employs one current and one voltage conveyor and only two diodes. It enables to process both low-voltage and low-current signals. Compared to the op amp based circuit, the proposed circuit is able to rectify signals up to 500 kHz and beyond with no or small distortion. Experimental measurements are performed that show the feasibility of the new precision full-wave rectifier.

关键词： analog processing circuits current conveyor instrumentation and measurements precision full-wave rectifier voltage conveyor

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