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International Conference on Instrumentation, Measurement, Computer, Communication and Control

作者： WANG Wei QIAN Liang Chih-Wei Liu Dept. of Electronics Engineering Shanghai Jiao Tong University Dept. of Electronics Engineering National Chiao Tung University

ISBN: (纸本)9781457713675

Underwater acoustic communication systems need Doppler compensation for the server Doppler effects. OFDM (Orthogonal Frequency Division Multiplexing) is widely applied in the underwater acoustic communication systems. FFT is the most computational kernels in the OFDM systems. By exploring the two typical digital signal processing kernels and other basic kernels, an ASIP (application specific instruction set processor) has been proposed. The proposed composite function unit can reach high MOPS in most DSP kernels with less read/write ports. Also, the proposed composite function unit reduce the memory access and register file access of the FFT, which is the bottleneck of the certain implementation of the FFT. The clock speed of the proposed ASIP can reach up to 600MHz under the CMOS 90nm technology.

关键词： Underwater Acoustic Communication Systems application specific instruction set processor Operation per Cycle Composite Function Unit

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An application specific instruction set processor Optimized for FFT

An Application Specific Instruction Set Processor Optimized ...

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54th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Wang, Wenxiang Li, Ling Zhang, Guangfei Liu, Dong Qiu, Ji Chinese Acad Sci Inst Comp Technol Beijing 100190 Peoples R China

ISBN: (纸本)9781612848570

This paper presents an application specific instruction set processor (ASIP) pruned for high-throughput and variable-length Fast Fourier Transform (FFT), which is a key component of various Orthogonal Frequency Division Multiplexing (OFDM)-based wireless communication standards. The ASIP executes dedicated FFT instructions to process two radix-4 or four radix-2 butterfly operations every clock cycle. Furthermore, a shuffle-embedded register file and a programmable memory access coprocessor are employed to tackle the memory access bottleneck and reduce power consumption. The implementation results show that our ASIP requires only 892 clock cycles for a 1024-point FFT, which outperforms TI TMS320C64x DSP and Tensilica ConnX ASIP by 6.74X and 2.03X, respectively. A test chip of the proposed ASIP was fabricated using CMOS 65nm process with the core area of 1.9mm(2). It consumes 85mW when it runs at the maximum frequency of 150MHz.

关键词： CMOS process Digital signal processing FFT Field-flow fractionation IEEE 802.16 Standards OFDM application specific instruction set processor application specific integrated circuits coprocessors fast Fourier transforms high-throughput instruction sets memory access bottleneck orthogonal frequency division multiplexing power consumption programmable memory access coprocessor shuffle-embedded register file variable-length fast Fourier transform wireless communication standards

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An application specific instruction set processor (ASIP) for Adaptive Filters in Neural Prosthetics

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IEEE-ACM TRANSACTIONS ON COMPUTATIONAL BIOLOGY AND BIOINFORMATICS 2015年第5期12卷 1034-1047页

作者： Xin, Yao Li, Will X. Y. Zhang, Zhaorui Cheung, Ray C. C. Song, Dong Berger, Theodore W. City Univ Hong Kong Dept Elect Engn Hong Kong Hong Kong Peoples R China Nanjing Univ Sci & Technol Sch Comp Sci & Engn Nanjing 210094 Jiangsu Peoples R China Univ So Calif Ctr Neural Engn Dept Biomed Engn Los Angeles CA 90089 USA

Neural coding is an essential process for neuroprosthetic design, in which adaptive filters have been widely utilized. In a practical application, it is needed to switch between different filters, which could be based on continuous observations or point process, when the neuron models, conditions, or system requirements have changed. As candidates of coding chip for neural prostheses, low-power general purpose processors are not computationally efficient especially for large scale neural population coding. application specific integrated circuits (ASICs) do not have flexibility to switch between different adaptive filters while the cost for design and fabrication is formidable. In this research work, we explore an application specific instruction set processor (ASIP) for adaptive filters in neural decoding activity. The proposed architecture focuses on efficient computation for the most time-consuming matrix/vector operations among commonly used adaptive filters, being able to provide both flexibility and throughput. Evaluation and implementation results are provided to demonstrate that the proposed ASIP design is area-efficient while being competitive to commercial CPUs in computational performance.

关键词： Neuroprosthetics neural coding adaptive filter application specific instruction set processor field-programmable gate array

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A High Performance Java Card Virtual Machine Interpreter based on an application specific instruction-set processor 17

A High Performance Java Card Virtual Machine Interpreter bas...

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17th Euromicro Conference on Digital System Design (DSD)

作者： Zilli, Massimiliano Raschke, Wolfgang Weiss, Reinhold Steger, Christian Loinig, Johannes Graz Univ Technol Inst Tech Informat A-8010 Graz Austria NXP Semicond Austria GmbH Gratkom Austria

ISBN: (纸本)9781479957934

Java Card is a Java running environment specific for smart cards. In such low-end embedded systems, the execution time of the applications is an issue of first order. One of the components of the Java Card Virtual Machine (JCVM) playing an important role in the execution speed is the bytecode interpreter. In Java systems the main technique for speeding-up the interpreter execution is the Just-In-Time compilation (JIT), but this resource consuming technique is inapplicable in systems with as restricted resources available as in smart cards. This paper presents a hardware/software co-design solution for the performance improvement of the interpreter. In the software domain, we adopted a pseudo-threaded code interpreter that allows a better run-time performance with a small amount of additional code. In the hardware domain, we proceeded moving parts of the interpreter into hardware, giving origin to a Java Card interpreter based on an application specific instruction set processor.

关键词： Smart card Java Card interpreter application specific instruction set processor

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A case study: Synthesis and exploration of instruction set design for application-specific symbolic computing

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JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 1998年第4期14卷 821-842页

作者： Huang, IJ Natl Sun Yat Sen Univ Inst Comp & Informat Engn Kaohsiung 804 Taiwan

The design of computer instruction sets has been mostly considered as being a manual process, due to complications between hardware and software, and the lack;of suitable design tools. The manual process limits understanding of the hardware/ software interface and tradeoffs. Motivated by this limitation, the design automation system ASIA (Automatic Synthesis for instruction-set Architecture) was developed to systematize the design process for instruction sets. This paper presents a case study of using ASIA in synthesis and design exploration for application specific Symbolic (Prolog) computing. instruction sets are optimized for given applications while maintaining their support for general Prolog execution. The results are compared with the VLSI-BAM processor, a manually-designed, general purpose instruction set processor for Prolog. The experiments show that: (1) the systematic and quantitative approach to instruction set design is feasible;(2) the design space of application-specific instruction sets consists of multiple dimensions across hardware and software, and ASIA is capable of exploiting such a complex design space and managing the hardware/software interactions;(3) the architectural properties of software applications vary significantly;therefore, (4) application specific instruction sets can provide better performance/cost tradeoff than can the general purpose instruction set processor in the context of specific application domains.

关键词： instruction set architecture synthesis application specific instruction set processor architectural analysis design exploration

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High-throughput bit processor for cryptography, error correction, and error detection

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MICROprocessorS AND MICROSYSTEMS 2018年 61卷 207-216页

作者： Huo Yuanhong Liu Dake Beijing Inst Technol Comp Sci & Technol Beijing 100081 Peoples R China Beijing Inst Technol Inst Applicat Specif Instruct Set Processors ASIP Beijing 100081 Peoples R China

The product lifetime (time-in-market) of a high-end embedded SoC (System-on-Chip) can be rather short due to possible design changes, leading to a highly expensive SoC redesign. Most of the SoC redesign are induced by the requirements for function changes of non-programmable ASIC modules. Plenty of the non-programmable ASIC modules are used for bit-wise algorithms. It is thus necessary to offer programmable/flexible VLSI designs for the bit-wise algorithms. In this paper, we propose a programmable ASIP design for four types of the bit-wise algorithms: block ciphers, stream ciphers, Reed-Solomon (RS) Codes, and Cyclic Redundancy Check (CRC). We achieve this via finding out the algorithm similarities and the optimal parallel degree (128-bit) among the four types of bit-wise algorithms. The flexibility of our design can enlarge the range of applications and extend the time-in-market of a SoC. Besides, our design achieves ASIC-like performance such as 25.6 Gb/s for AES encryption, 17.6 Gb/s for RS(255,239) decoding, and 281.6 Gb/s for CRC calculation, etc with 0.19 mm(2) (28 nm) silicon area. Finally, we show that the performance of our design is sufficient for high-speed communication protocols like IEEE 802.11ad when running real-time AES, RS, and CRC simultaneously.

关键词： application specific instruction set processor Software defined radio Cryptographic processor VLSI (Very large-scale integration)

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Area and energy efficient 802.11ad LDPC decoding processor

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ELECTRONICS LETTERS 2015年第4期51卷 339-340页

作者： Li, Meng Lee, Youngjoo Huang, Yanxiang Van der Perre, Liesbet IMEC Dept Circuits & Syst Leuven Belgium

The design of multi-Gbit/s low-density parity-check code (LDPC) decoders has become a hot topic in recent years to meet the growing demand of the transformation towards 4G. An area and energy efficient multi-Gbit/s LDPC decoder engine with a fully paralleled layered architecture based on an application-specific instruction set processor (ASIP) using Synopsys IP designer is presented. When the ASIP core is instantiated for 802.11ad, it achieved a throughput of up to 7 Gbit/s at three iterations with a latency of 95 ns, a record energy efficiency of 2.5 pJ/bit/iteration and an area efficiency of 54.5 Gbit/s/sq-m in CMOS 28 nm technology for the 1/2 rate, showing it to be competitive against published ASIC solutions.

关键词： parity check codes wireless LAN 802.11ad LDPC decoding processor ASIC solutions ASIP ASIP core Synopsys IP designer application specific instruction set processor low density parity check codes multiGbps LDPC decoder engine paralleled layered architecture

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Hardware/software co-design for a high-performance Java Card interpreter in low-end embedded systems

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MICROprocessorS AND MICROSYSTEMS 2015年第8期39卷 1076-1086页

作者： Zilli, Massimiliano Raschke, Wolfgang Weiss, Reinhold Loinig, Johannes Steger, Christian Graz Univ Technol Inst Tech Informat A-8010 Graz Austria NXP Semicond Austria GmbH Gratkorn Austria

Java Card is a Java running environment specific for smart cards. In such low-end embedded systems, the execution time of the applications is an issue of first order. One of the components of the Java Card Virtual Machine (JCVM) playing an important role in the execution speed is the bytecode interpreter. In Java systems the main technique for speeding-up the interpreter execution is the Just-In-Time compilation am, but this resource consuming technique is inapplicable in systems with as restricted resources available as in smart cards. This paper presents a hardware/software co-design solution for the performance improvement of the interpreter. In the software domain, we adopted a pseudo-threaded code interpreter that allows a better run-time performance with a small amount of additional code. In the hardware domain, we proceeded moving parts of the interpreter into hardware, giving origin to a Java Card interpreter based on an application specific instruction set processor. (c) 2015 Elsevier B.V. All rights reserved.

关键词： Hardware/software co-design Smart card Java Card Java interpreter Hardware-supported interpreter application specific instruction set processor

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Design and implementation of an ASIP for SHA-3 hash algorithm

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INTERNATIONAL JOURNAL OF INFORMATION AND COMPUTER SECURITY 2022年第3-4期17卷 285-309页

作者： Mehrabani, Yavar Safaei Ataie, Roghayeh Shafiabadi, Mohammad Hossein Ghasempour, Abolghasem Islamic Azad Univ Dept Comp Engn North Tehran Branch Tehran Iran Univ Jiroft Dept Elect Engn Jiroft Iran Islamic Azad Univ Dept Comp Engn Islam Shahr Branch Tehran Iran

In recent years, application specific instruction set processor (ASIP) has attracted many researchers attention. These processors resemble application specific integrated circuits (ASICs) and digital signal processors (DSPs) from the performance and flexibility point of view, respectively. In other words, ASIP makes compromise between performance and flexibility criteria. The SHA-3 hashing algorithm has been introduced as the safest and the newest algorithm in 2015 as a global standard. In this paper, a processor with specific instruction set is designed and implemented with regard to variant execution steps of this algorithm. In order to do the modelling and simulation of the processor, we have used the VHDL hardware description language and the ModelSim SE 6.1 tool. Moreover, in order to implement it on a field programmable gate array (FPGA) platform we have used the Xilinx ISE 10.1 tool. The implemented processor has 213.356 MHz operating frequency and 3.004 Mbps throughput.

关键词： application specific instruction set processor ASIP processor instruction set architecture ISA hash SHA-3 algorithm

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Design of a Multi-Core Hardware Architecture for Consensus-Based MIMO Detection Algorithms 50

Design of a Multi-Core Hardware Architecture for Consensus-B...

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50th Asilomar Conference on Signals, Systems, and Computers (ASILOMARSSC)

作者： Tscherkaschin, Konstantin Knoop, Benjamin Rust, Jochen Paul, Steffen Univ Bremen Inst Elect & Microelect ITEM me Bremen Germany

ISBN: (纸本)9781538639542

Consensus-based algorithms are a welcome approach to establish cooperative communication systems. In this work, it has been utilized to present a hardware architecture for distributed data detection in a receiver with several sensor nodes on an easily scalable regular network. Additionally, it is capable to detect the transmitted message even if a single sensor node fails to operate. On top of that, the processing is executed on vector-based application specific instruction set processors as processing cores. This makes it very flexible for reconfiguring the network and reprogramming of the algorithm, though being highly performant.

关键词： Robustness Cooperative Communication Consensus MIMO Regular Ring Topology application specific instruction set processor

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