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36th Annual Conference of the IEEE Industrial-Electronics-Society/4th IEEE International Conference on E-Learning in Industrial Electronics/IES Industry Forum

作者： Moreno-Berengue, Marc Talavera, Guillermo Rodriguez-Alsina, Aitor Carrabina, Jordi Univ Autonoma Barcelona Bellaterra Spain

ISBN: (纸本)9781424452262

Multimedia embedded systems require high performance specific computation to process the large among of data that characterizes the multimedia domain at low energy consumption due to battery life. Different optimizations at different levels can considerably improve performance and energy consumption and, after that, the address generation becomes the new performance bottleneck. This paper shows a custom-configurable address generation unit design which extends an application specific instruction set processor (ASIP) to boost the address calculations, improving performance and reducing the energy consumption around 27%. The main innovation of our work resides in a new custom-configurable AGU design which can be automatically implemented and directly connected to the ASIP data-path. This AGU design has a fast interface which allows reading one address in only one cycle and one instruction, and calculates new values without stopping the processor. The presented design can easily be implemented in broad range of ASIPs.

关键词： Address generation optimization application specific instruction set processors soft-core embedded multimedia

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Reconfigurable architectures and processors for real-time video motion estimation

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2007年第4期2卷 191-205页

作者： Dias, Tiago Roma, Nuno Sousa, Leonel Ribeiro, Miguel INESC ID IST SiPS P-1000029 Lisbon Portugal INESC ID ISEL SiPS P-1000029 Lisbon Portugal INESC ID SiPS P-1000029 Lisbon Portugal

With the recent proliferation of multimedia applications, several fast block matching motion estimation algorithms have been proposed in order to minimize the processing time in video coding. While some of these algorithms adopt pre-defined search patterns that directly reflect the most probable motion structures, other data-adaptive approaches dynamically configure the search pattern to avoid unnecessary computations and memory accesses. Either of these approaches leads to rather difficult hardware implementations, due to their configurability and adaptive nature. As a consequence, two different but quite configurable architectures are proposed in this paper. While the first architecture reflects an innovative mechanism to implement motion estimation processors that support fast but regular search algorithms, the second architecture makes use of an application specific instruction set processor (ASIP) platform, capable of implementing most data-adaptive algorithms that have been proposed in the last few years. Despite their different natures, these two architectures provide highly configurable hardware platforms for real-time motion estimation. By considering a wide set of fast and adaptive algorithms, the efficiency of these two architectures was compared and several motion estimators were synthesized in a Virtex-II Pro XC2VP30 FPGA from Xilinx, integrated within a ML310 development platform. Experimental results show that the proposed architectures can be easily reconfigured in run-time to implement a wide set of real-time motion estimation algorithms.

关键词： Motion estimation Fast search algorithms Video coding Reconfigurable devices application specific instruction set processors

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Implementation-aware selection of the custom instruction set for extensible processors

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MICROprocessors AND MICROSYSTEMS 2014年第7期38卷 681-691页

作者： Yazdanbakhsh, Amir Kamal, Mehdi Fakhraie, Sied Mehdi Afzali-Kusha, Ali Safari, Saeed Pedram, Massoud Univ Tehran Sch Elect & Comp Engn Tehran 14174 Iran Univ So Calif EE Dept Los Angeles CA 90089 USA

This paper presents an approach for incorporating the effect of various logic synthesis options and logic level implementations into the custom instruction (CI) selection for extensible processors. This effect translates into the availability of a piecewise continuous spectrum of delay versus area choices for each CI, which in turn influences the selection of the CI set that maximizes the speedup per area cost (SPA) metric. The effectiveness of the proposed approach is evaluated by applying it to several benchmarks and comparing the results with those of a conventional technique. We also apply the methodology to the existing serialization algorithms aimed at relaxing register file constraints in multi-cycle custom instruction design. The comparison shows considerable improvements in the speedup per area compared to the custom instruction selection algorithms under the same area-budget constraint. (C) 2014 Elsevier B.V. All rights reserved.

关键词： Extensible processor Design space exploration Hardware/software codesign application specific instruction set processors Microarchitecture

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Design space exploration for DSP applications using the ASIP development system PEAS-III

Design space exploration for DSP applications using the ASIP...

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IEEE International Conference on Acoustics, Speech, and Signal Processing

作者： Kobayashi, S Mita, K Takeuchi, Y Imai, M Osaka Univ Grad Sch Engn Sci Dept Informat & Math Sci Osaka Japan

ISBN: (纸本)0780374029

This paper describes rapid design space exploration for DSP applications using the PEAS-III system, which is a configurable processor development environment for application domain specific embedded systems. First, a compiler generation method, which is one of the key technologies in the PEAS-III system, is proposed. The target compiler is generated from the same information as used for the synthesizable HDL generation of the target processor. Using the PEAS-III system, not only the processor HDL description but also its target compiler are generated. Therefore, execution time which is computed from execution cycles of applications and generated processor's frequency can be rapidly evaluated. Experimental results showed that the trade-offs between area and performance of processors for DCT and FIR filter applications were analyzed in 4.1 hours and the optimal processor was selected under the design constraint by using generated compilers and processors.

关键词： digital signal processing chips embedded systems compiler generators hardware description languages discrete cosine transforms FIR filters integrated circuit layout digital integrated circuits high level synthesis application specific integrated circuits electronic design automation design space exploration DSP applications application specific instruction set processors ASIP application specific integrated processor PEAS-III configurable processor development environment embedded systems compiler generation method synthesisable HDL generation DCT FIR filter

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Automatic Generation of Custom SIMD instructions for Superword Level Parallelism

Automatic Generation of Custom SIMD Instructions for Superwo...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Kim, Taemin Hoskote, Yatin Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9783981537024

application specific instruction-set processors (ASIPs) have drawn significant attention from System-on-a-Chip (SoC) community due to the capability of fine grain flexibility and customizability. In order to maximize the benefit of ASIP, automatic instruction set extension (ISE) is required. In the past decade, there have been plethora of researches on automatic ISE for custom scalar instruction. However, due to increasing usage of SIMD instructions to exploit data level parallelism (DLP) that exists both across loop iterations and within a basic block called Superword Level Parallelism (SLP), automatic generation of custom SIMD instructions is the inevitable direction of automatic ISE. In this paper, we propose an algorithm that automatically generates custom SIMD instructions from a set of custom scalar instructions to exploit SLP. We have demonstrated 52.4% and 30.8% performance improvement on average over base instruction set and additional custom scalar instructions, respectively.

关键词： instruction sets system-on-chip application specific instruction set processors automatic generation custom SIMD instructions custom scalar instruction data level parallelism fine grain flexibility superword level parallelism system on a chip Clustering algorithms Parallel processing Program processors Registers Silicon Vectors

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On the Feasibility of using FPGA's for Efficient Topology Optimization 26

On the Feasibility of using FPGA's for Efficient Topology Op...

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26th Euromicro Conference on Digital System Design (DSD) / 49th Euromicro Conference on Software Engineering and Advanced applications (SEAA)

作者： Hesse, Kasper Schoeberl, Martin Aage, Niels Traeff, Erik Tech Univ Denmark DTU Compute Lyngby Denmark

ISBN: (纸本)9798350344196

Topology Optimization is a class of structural optimization problems, where the classical goal is to find the best layout of a structure ensuring that it can withstand a set of prescribed forces, while being as light as possible. Since this class of optimization problems are computationally expensive, a vast amount of research is directed at how to increase the speed at which these problems can be solved. Previous work on accelerating topology optimization problems includes designing more efficient algorithmic approaches and better utilizing hardware resources. However, to the best of our knowledge, no previous attempts have been made to accelerate topology optimization using a hardware accelerator implemented on an FPGA. This paper presents a hardware accelerator for topology optimization, designed to solve compliance minimization problems in three dimensions. The accelerator is implemented as an application-specific instruction set processor, using a custom instruction set architecture designed specifically for the minimum compliance problem. The developed accelerator is able to solve problems 4.8-8.2 times faster than a modern computer, while operating at a fraction of the clock frequency. Although the current accelerator has only been proven to work on coarse meshes, it is reasonable to assume that the speedup will also carry over to larger optimization problems. This indicates that FPGA-based acceleration of topology optimization problems is viable.

关键词： FPGA Topology Optimization Fixed point arithmetic application specific instruction set processors

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From ASIC to ASIP: The next design discontinuity

From ASIC to ASIP: The next design discontinuity

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20th IEEE International Conference on Computer Design

作者： Keutzer, K Malik, S Newton, AR Univ Calif Berkeley Dept EECS Berkeley CA 94720 USA

ISBN: (纸本)0769517013

A variety of factors is making it increasingly difficult and expensive to design and manufacture traditional application specific Integrated Circuits (ASICs). This has started a significant move towards the use of programmable solutions of various forms - increasingly referred to as programmable platforms. For the platform manufacturer, programmability provides higher volume to amortize design and manufacturing costs, as the same platform can be used over multiple related applications, as well as over generations of an application. For the application implementer, programmability provides a lower risk and shorter time-to-market implementation path. The flexibility provided by programmability comes with a performance and power overhead. This can be significantly mitigated by using application specific platforms, also referred to as application specific instruction set processors (ASIPs). This paper details the reasons for this significant change in application implementation philosophy, provides illustrative contemporary evidence of this change, examines the space of application specific platforms, outlines fundamental problems in their development, and finally presents a methodology to deal with this changing design style.

关键词： application specific integrated circuits application specific instruction set processors ASIC ASIP programmable platforms design methodology

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