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Design of approximate circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN circuits AND SYSTEMS 2018年第4期8卷 746-757页

作者： Camus, Vincent Cacciotti, Mattia Schlachter, Jeremy Enz, Christian Ecole Polytech Fed Lausanne Integrated Circuits Lab CH-1015 Lausanne Switzerland

This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e., critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal and controlled behavioral change. This technique is applied to an approximate adder architecture, called the Carry Cut-Back Adder (CCBA), in which high-significance stages can cut the carry propagation chain at lower-significance positions. This lightweight approach prevents the logic activation of the carry chain, improving performance and energy efficiency while guaranteeing low worst-case errors. A design methodology is presented along with implementation, error optimization, and design-space minimization. The CCBA is proven capable of extremely high accuracy while displaying significant circuit savings. For a worst case precision of 99.999%, energy savings up to 36% are demonstrated compared with exact adders. Finally, an industry-oriented comparison of 32-bit approximate and truncated adders is carried out for mean and worst-case relative errors. The CCBA outperforms both state-of-the-art and truncated adders for high-accuracy and low-power circuits, confirming the interest of the proposed concept to help building highly-efficient approximate or precision-scalable hardware accelerators.

关键词： Low-power digital circuits timing optimization false timing paths approximate circuits approximate adders speculative adders

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Logic Synthesis of approximate circuits

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED circuits AND SYSTEMS 2020年第10期39卷 2503-2515页

作者： Venkataramani, Swagath Kozhikkottu, Vivek J. Sabne, Amit Roy, Kaushik Raghunathan, Anand Purdue Univ Sch Elect & Comp Engn W Lafayette IN 47907 USA

The ability of several important application domains to tolerate inexactness or approximations in a large fraction of their computations has lead to the advent of approximate computing, a new design paradigm that exploits the intrinsic error-resilient nature to optimize computing platforms for energy and performance. A promising approach to approximate computing is to design approximate circuits, or circuit implementations that are highly efficient but differ in functionality from their original specifications subject to a prespecified quality constraint. While a slew of manual design techniques for approximate circuits have demonstrated their significant potential, a key requirement for their mainstream adoption is to develop automatic methodologies and tools that are general and scalable to any given circuit and quality specification. In this article, we propose SALSA, a systematic methodology for automatic logic synthesis of approximate circuits. Given a golden RTL specification of a circuit and a quality constraint that defines the amount of error that may be introduced in the implementation, SALSA synthesizes an approximate version of the circuit that adheres to the prespecified quality bounds. We make two key contributions: 1) the rigorous formulation of the problem of approximate logic synthesis (ALS), enabling the generation of circuits that is corrected by construction and 2) mapping the problem of approximate synthesis into an equivalent traditional logic synthesis problem, thereby allowing the capabilities of existing synthesis tools to be fully utilized for ALS. In order to achieve these benefits, SALSA forms a virtual quality constraint circuit (QCC) that encodes the quality constraints using logic functions called Q-functions. It then captures the flexibility that engendered by them as approximation don't cares (ADCs), which are used for circuit simplification using traditional don't care-based optimization techniques. We utilized SALSA to automaticall

关键词： Tools Measurement Optimization approximate computing Logic functions Automation Systematics approximate circuits approximate computing error resilience logic synthesis low power design

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cecApprox: Enabling Automated Combinational Equivalence Checking for approximate circuits

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IEEE TRANSACTIONS ON circuits AND SYSTEMS I-REGULAR PAPERS 2024年第7期71卷 3282-3293页

作者： Jha, Chandan Kumar Hassan, Muhammad Drechsler, Rolf Univ Bremen Inst Comp Sci D-28359 Bremen Germany DFKI German Res Ctr Artificial Intelligence D-28359 Bremen Germany

approximate circuits have become ubiquitous in error-resilient applications. Given their widespread use, formal verification of these approximate designs is essential. Recently, there have been attempts that use formal verification techniques based on Boolean Satisfiability (SAT) Methods and Binary Decisions Diagrams (BDDs) to perform formal error analysis. These methods guarantee that the designed approximate circuits satisfy the error metrics, e.g., Mean Square Error (MSE), etc. However, in certain approximate circuits tailored for a particular input data distribution, only performing error analysis is not enough. In addition to error metrics, the functional specifications in these approximate circuits should also be satisfied. Otherwise, it can lead to a larger-than-expected deterioration in the output quality. In this work, for the first time, we alleviate this issue by proposing an automated formal verification methodology, cecApprox, that guarantees the approximate circuit matches the functional specification. This is crucial for circuits that are tailored for a particular input distribution. We show that in the designs where the structure is preserved, the corrected circuit can be generated from the approximate circuit. This corrected circuit can then be formally verified by performing combinational equivalence checking with the exact circuit as the golden reference. If the corrected circuit is equivalent to the exact circuit, it guarantees that the approximate circuit matches the given functional specification in addition to error metrics. Hence, the cecApprox methodology complements the formal error analysis method. We show the efficacy of cecApprox by generating and formally verifying millions of different 8-bit and 16-bit structural preserved approximate adders and multipliers using combinational equivalence checking.

关键词： approximate circuits combinational equivalence checking adders multipliers error analysis and binary decision diagrams Formal verification Boolean satisfiability

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Detailed insight into approximate circuits with error-responsive information flow tracking

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IT-INFORMATION TECHNOLOGY 2024年第4-5期66卷 147-158页

作者： Schammer, Lutz Martino, Gianluca Najafi, Amir Garcia-Ortiz, Alberto Fey, Goerschwin Hamburg Univ Technol Hamburg Germany Univ Bremen Bremen Germany

A significant challenge hindering the widespread adoption of approximate hardware units is the complexity associated with test and error evaluation. We address this issue by extending Information Flow Tracking (IFT) for hardware designs to accommodate approximate units. Unlike conventional IFT approaches, our system employs a dynamic, error-responsive tag-based mechanism that facilitates tracking the error characteristics and their propagation within approximate units. Such an approach is vital in the domain of approximate computing, where uncommon yet substantial errors, such as those found in Equal Segmentation Adders (ESA), can markedly influence computation accuracy and reliability. By focusing on the dynamic nature of errors and their traceability, our methodology supports understanding the effects of approximation errors, thereby promoting their broader utilisation in various applications. The results of our study demonstrate the potential of analysing error propagation in approximate designs.

关键词： IFT approximate circuits design understanding

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Parallel Multi-Objective Evolutionary Design of approximate circuits 15

Parallel Multi-Objective Evolutionary Design of Approximate ...

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17th Genetic and Evolutionary Computation Conference (GECCO)

作者： Hrbacek, Radek Brno Univ Technol Fac Informat Technol CS-61090 Brno Czech Republic

ISBN: (纸本)9781450334723

Evolutionary design of digital circuits has been well established in recent years. Besides correct functionality, the demands placed on current circuits include the area of the circuit and its power consumption. By relaxing the functionality requirement, one can obtain more efficient circuits in terms of the area or power consumption at the cost of an error introduced to the output of the circuit. As a result, a variety of trade-offs between error and efficiency can be found. In this paper, a multi-objective evolutionary algorithm for the design of approximate digital circuits is proposed. The scalability of the evolutionary design has been recently improved using parallel implementation of the fitness function and by employing spatially structured evolutionary algorithms. The proposed multi-objective approach uses Cartesian Genetic Programming for the circuit representation and a modified NSGA-II algorithm. Multiple isolated islands are evolving in parallel and the populations are periodically merged and new populations are distributed across the islands. The method is evaluated in the task of approximate arithmetical circuits design.

关键词： Cartesian Genetic Programming Parallel Evolutionary Algorithms Multi-objective Optimization Cluster Combinational Circuit Design approximate circuits

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Special Session Paper: An Efficient Hardware Design for Cerebellar Models using approximate circuits 12

Special Session Paper: An Efficient Hardware Design for Cere...

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International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

作者： Jiang, Honglan Liu, Leibo Han, Jie Univ Alberta Edmonton AB Canada Tsinghua Univ Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781450351850

The superior controllability of the cerebellum has motivated extensive interest in the development of computational cerebellar models. Many models have been applied to the motor control and image stabilization in robots. Often computationally complex, cerebellar models have rarely been implemented in dedicated hardware. Here, we propose an efficient hardware design for cerebellar models using approximate circuits with a small area and a low power. Leveraging the inherent error tolerance in the cerebellum, approximate adders and multipliers are carefully evaluated for implementations in an adaptive filter based cerebellar model to achieve a good tradeoff in accuracy and hardware usage. A saccade system, whose vestibulo-ocular reflex (VOR) is controlled by the cerebellum, is simulated to show the applicability and effectiveness of the proposed design. Simulation results show that the approximate cerebellar circuit achieves a similar accuracy as an exact implementation, but it saves area by 29.7% and power by 37.3%.

关键词： Cerebellar model approximate circuits multiplier adder

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Formal Methods for Exact Analysis of approximate circuits

Formal Methods for Exact Analysis of Approximate Circuits

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作者： Vašíček, Zdeněk Brno University of Technology

approximate circuits are digital circuits that are intentionally designed in such a way that the specification is violated in terms of functionality in order to obtain some improvements in power consumption, performance or area, in comparison with fully functional circuits. To design the approximate circuits, the synthesis tools rely on the availability of a procedure checking, whether the synthesized circuits meet a specification and/or provides information about circuit quality. Compared to the traditional circuit design flow, the nature of the approximate circuits involves replacing the strict functional equivalence checking with a more advanced approach that enables us to quantify or guarantee the degree of similarity. The most common technique is to employ a circuit simulator for analysing responses for all input vectors. This approach allows us to simultaneously perform checking and quality assessment, but the exhaustive enumeration of the input vectors is tractable only for a small number of inputs. To avoid excessive run-times, a subset of all possible input vectors is typically used for complex circuits. This causes us, however, to lose the ability to guarantee that the quality of the synthesized circuits is within an acceptable range given in the specification. The main goal of this paper is to show how to adopt formal methods such as binary decision diagrams and satisfiability solvers for exhaustive analysis of approximate circuits without explicit enumeration of all input vectors. We survey the methods for exact computation of the most important error parameters used in the context of approximate computing, propose improved algorithms and provide a detailed analysis of their performance. The methods are benchmarked on a large set of key approximate circuits consisting of nearly 2,000 unique arithmetic instances with 8-, 12-, 16-, and 32-bit operands which helps us to identify the best algorithm and method for computation of a desired error parameter.

关键词： approximate computing approximate circuits binary decision diagrams error metrics error analysis formal methods satisfiability solvers quality assessment

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Formal Methods for Exact Analysis of approximate circuits

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IEEE ACCESS 2019年 7卷 177309-177331页

作者： Vasicek, Zdenek Brno Univ Technol IT4Innovat Ctr Excellence Brno 60190 Czech Republic

关键词： approximate computing approximate circuits binary decision diagrams error metrics error analysis formal methods satisfiability solvers quality assessment

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An efficient VLSI architecture of 2-D finite impulse response filter using enhanced approximate compressor circuits

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INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2021年第11期49卷 3653-3668页

作者： Odugu, Venkata Krishna Narasimhulu, Venkata C. Prasad, Satya K. JNTUK ECE Dept Kakinada India CVR Coll Engn ECE Dept Hyderabad India Lords Inst Engn & Technol ECE Dept Hyderabad India

The very large-scale integration (VLSI) design-based architectures of 2-D filters must have low power consumption and high speed rather than accuracy for image processing applications. The inexact computations reduce the delay, area, and power in arithmetic architectures, and utilizing this advantage an approximation can be introduced in 2-D digital filters. In this work, circular symmetry is adopted to optimize the 2-D finite impulse response (FIR) filter architecture, and it is implemented using imprecise multipliers and approximate compressors with acceptable accuracy. The exact 4:2 compressor is modified into an approximate 4:2 compressor by ignoring few inputs. Hence, hardware requirement and delay parameters are improved. The proposed compressor is designed by mixed logic rather than complete complementary metal-oxide semiconductor (CMOS) logic. The dual value logic (DVL), transmission gate logic (TGL), and CMOS mixed logic gates are used to decrease the number of transistors in the circuits. The proposed compressors are used in the approximate Dadda multiplier (ADM). The ADMs are utilized to implement the 2-D FIR filter architecture. The designed filter is coded in Verilog and implemented using field programmable gate array (FPGA). The hardware utilization is analyzed and compared with exact 2-D FIR filters. Next, the proposed architecture is synthesized using Cadence genus tools, and physical design is carried out by Cadence Innovus tools in 45-nm CMOS technology. The final physical design layout-area, power, and delay reports are correlated with existing state-of-artworks. It is found that the proposed 2-D FIR filter outperforms the existing works.

关键词： 2-D FIR filter 4 2 compressor circuits approximate circuits Dadda multiplier dual value logic (DVL) low power symmetry in filters transmission gate logic (TGL)

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An efficient hardware design for cerebellar models using approximate circuits: special session paper 17

An efficient hardware design for cerebellar models using app...

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Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion

作者： Honglan Jiang Leibo Liu Jie Han University of Alberta Edmonton AB Canada Tsinghua University Beijing China

ISBN: (纸本)9781450351850

关键词： multiplier cerebellar model approximate circuits adder

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