检索结果-内蒙古大学图书馆

A High-Throughput VLSI Architecture Design of arithmetic encoder in JPEG2000

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2015年第2期81卷 227-247页

作者： Di, Zhixiong Hao, Yue Shi, Jiangyi Ma, Peijun Southwest Jiaotong Univ Sch Informat Sci & Technol Chengdu Sichuan Peoples R China Xidian Univ State Key Discipline Lab Wide Band Gap Semicond T Xian 710071 Peoples R China

The arithmetic encoder (AE) is a throughput bottleneck of the entire JPEG2000 encoding system. But its sequential nature leads to a difficulty to improve its throughput. To overcome this bottleneck, a high-throughput AE capable of encoding one symbol per clock is proposed. First, the correlations between the sequential pairs of context and its decision are analyzed. Moreover, the burst number of CX and the burst number of the index value are studied. Due to these analyses, a conclusion is drawn in order to prevent the AE from stalling when the burst number of the context is larger than one. Based on this conclusion, an "index-arbiter" method is introduced, which increased the throughput greatly. Furthermore, the probabilities of different adjusting manners for the interval register A and code register C before renormalization are given. On the basis of these data, a detector of leading-zero is proposed to simplify the renormalization procedure. Finally, the total number and the max burst number of the two-byte emission are given. According to these results, a FIFO size of 43*4 is introduced to prevent the pipeline from pause when two-byte emission occurs. The proposed architecture is synthesized with TSMC0.18 mu m HS technology library of ARM Company. The implementation result shows that the throughput of the proposed architecture is 547Msymbols/s with an area of 79,012.84 mu m(2). Compared with the paper Rhu and Park (IEEE Transactions on Circuits and Systems for Video Technology, 20(3),446-451, 2010), the throughput has been increased by 37 %.

关键词： VLSI JPEG2000 arithmetic encoder MQ-encoder

来源：评论

学校读者我要写书评

暂无评论

High-Throughput and Low-Power Architectures for the AV1 arithmetic encoder 34

High-Throughput and Low-Power Architectures for the AV1 Arit...

引用

34th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Bitencourt, Tulio Pereira Livi Ramos, Fabio Luis Bampi, Sergio Univ Fed Rio Grande do Sul Informat Inst Porto Alegre RS Brazil Fed Univ Pampa Comp Engn Bage Brazil

ISBN: (纸本)9781665421706

With the emerging interest in video-on-demand systems, streaming service providers shall acclimate their systems to decrease the global Internet infrastructure impact caused by videos. Video coding standards are presented as a powerful but complex solution for this problem. Hence, to tackle these tools' complexity and allow a better codification flow, hardware designs arise as options for decreasing the bottleneck of video-on-demand systems. This paper presents a hardware architecture, named AE-AV1, that aims to entirely execute the arithmetic encoding process of the AV1 codec while achieving enough throughput rate for an ultra-high performance (i.e., 8K@120fps real-time codification). Moreover, this document also propounds the LP-AE-AV1 architecture, which represents a low-power version of the AE-AV1.

关键词： AV1 video coding hardware architecture arithmetic encoder low-power

来源：评论

学校读者我要写书评

暂无评论

Power-Throughput Trade-off Analysis for a Novel Multi-Boolean AV1 arithmetic encoder Design

Power-Throughput Trade-off Analysis for a Novel Multi-Boolea...

引用

Picture Coding Symposium (PCS)

作者： Bitencourt, Tulio Pereira Livi Ramosy, Fabio Luis Bampi, Sergio Univ Fed Rio Grande do Sul PGMICRO Porto Alegre RS Brazil Fed Univ Pampa Bage RS Brazil EnSilica Brasil Ltd Porto Alegre RS Brazil

ISBN: (纸本)9781665492577

The efficient and royalties-free video coding format AV1 was released in 2018 to cope with ultra-high-resolution video processing (e.g., 8K), avoiding the burden of royalty fees. The AV1 arithmetic encoding process, which is seen as a bottleneck due to its difficulty to work with parallelization, relies upon two primary operations: CDF Operation and Boolean Operation. This work presents a proposal and analysis of a novel fashion to parallelize the Boolean Operation of the AV1 arithmetic encoding block to achieve higher throughput rates, at the same time considering the power consumption to be at a compromise level. Furthermore, a novel design named MB-AV1, which utilizes the parallel Boolean approach and is able to accomplish 8K real-time video processing, is introduced.

关键词： AV1 video coding arithmetic encoder hardware design VLSI architectures

来源：评论

学校读者我要写书评

暂无评论

Design of high speed arithmetic encoder

Design of high speed arithmetic encoder

引用

7th International Conference on Solid-State and Integrated Circuits Technology

作者： Mei, KZ Zheng, NN Yao, J Liu, YH Xian Jiaotong Univ Inst Artificial Intelligence & Robot Xian 710049 Peoples R China

ISBN: (纸本)078038511X

Focusing on the problem of path waiting or circular that existed in updating of context table and the Renorme and Byteout procedure in the realization of the conventional arithmetic encoder in JPEG2000, 3-step architecture is used on FPGA to get high speed encoding. A method of updating CX table is proposed;and a circuit with short delay is also implemented to detect the left zeros of A-register. Multiplexers are adopted to accelerate the random left shift operation, and parallel processing based on data dependency is used to optimize RTL code to shorten the main critical path, the updating logic of context table is last fully discussed. Experimental result shows the encoder can work up to 107MHz on Altera's EPIS25B672C7 and the critical path is 4.6 ns synthesized in synopsys DC by TSMC.25um library.

关键词： arithmetic encoder pipeline critical path JPEG2000

来源：评论

学校读者我要写书评

暂无评论

Design of high speed arithmetic encoder

Design of high speed Arithmetic Encoder

引用

2004 7th International Conference on Solid-State and Integrated Circuits Technology（ICSICT 2004）

作者： Mei Kuizhi,Zheng Nanning,Yao Ji,Liu Yuehu (The Institute of Artificial Intelligence and Robotics,Xi'an Jiaotong University,Xi'an 710049,China)

Focusing on the problem of path waiting or circular that existed in updating of context table and the Renorme and Byteout procedure in the realization of the conventional arithmetic encoder in JPEG2000,3-step pipeline architecture is used on FPGA to get high speed encoding.A method of updating CX table is proposed;and a circuit with short delay is also implemented to detect the left zeros of *** are adopted to accelerate the random left shift operation,and parallel processing based on data dependency is used to optimize RTL code to shorten the main critical path,the updating logic of context table is last fully discussed. Experimental result shows the encoder can work up to 107MHz on Altera's EP1S25B672C7 and the critical path is 4.6 ns synthesized in synopsys DC by TSMC.25um library.

关键词： arithmetic encoder pipeline critical path JPEG2000

来源：评论

学校读者我要写书评

暂无评论

VLSI design of a high-speed and area-efficient JPEG2000 encoder

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2007年第8期17卷 1065-1078页

作者： Mei, Kuizhi Zheng, Nanning Huang, Chang Liu, Yuehu Zeng, Qiang Xi An Jiao Tong Univ Inst Artificial Intelligence & Robot Xian 710049 Peoples R China Viatech Corp Shanghai 201203 Peoples R China

A high-speed VLSI design of an area-efficient JPEG2000 encoder is given. Recursive multilevel 2-D discrete wavelet transform (DWT) architecture with dual buffers is proposed to reduce the wavelet coefficients memory to 1/4 tile size, prerate allocation is used to reduce the compressed code memory to 3/4 tile size. A highly pipelined and parallelism implementation of line-based I-level DWT is proposed using two line-buffers in 513 wavelet type and its input speed is. up to 2 samples/cycle;code block based address mapping in access wavelet coefficients memory, concurrent state variables generation, and multiple parallel and pipeline coding methods are used in the bit plane encoder (BPE) which encodes on average at 40.5M samples/s at 100 MHz with no memory used;the conditional two-symbol pipeline arithmetic encoder (AE) encodes at 1.3 symbols/cycle. Parallel units in BPE and buffer control between BPE and AE are optimally implemented with low cost without performance loss. Byte representation of rate-distortion slope used reaches a near optimal implementation of post-coding rate distortion in Tier2 with low cost. The compressed file generated by the encoder is fully compatible with ISO/IEC FCD15444-1[1]. The encoder is verified on field-programmable gate array platform with a direct interface to digital video input with tile size 256 x 256 and code block size 32 x 16. The resulting input sampling rate is up to 58 M samples/s when Tierl operates at 100 MHz. Difference of the peak signal-to-noise ratio of images compressed by our encoder and JasPer [2] is less than 0.2 dB;when the compression ratio is greater than 1 bps. Equivalent NAND2 gates synthesized are 90.6 K and on-chip RAM size is 626.75 kb. Unlike other designs the proposed design of JPEG2000 encoder has high compression quality as well as high speed and area-efficiency.

关键词： arithmetic encoder bit plane encoder (BPE) discrete wavelet transform (DWT) field programmable gate array (FPGA) JPEG2000 encoder Tier2 VLSI

来源：评论

学校读者我要写书评

暂无评论

Compression of Graphical Structures: Fundamental Limits, Algorithms, and Experiments

引用

IEEE TRANSACTIONS ON INFORMATION THEORY 2012年第2期58卷 620-638页

作者： Choi, Yongwook Szpankowski, Wojciech J Craig Venter Inst Rockville MD 20850 USA Purdue Univ Dept Comp Sci W Lafayette IN 47907 USA

Information theory traditionally deals with "conventional data," be it textual data, image, or video data. However, databases of various sorts have come into existence in recent years for storing " unconventional data" including biological data, social data, web data, topographical maps, and medical data. In compressing such data, one must consider two types of information: the information conveyed by the structure itself, and the information conveyed by the data labels implanted in the structure. In this paper, we attempt to address the former problem by studying information of graphical structures (i.e., unlabeled graphs). As the first step, we consider the Erdos-Renyi graphs G(n,p) over n vertices in which edges are added independently and randomly with probability p. We prove that the structural entropy of G(n,p) is (n 2) h(p) - log n! + o(1) = (n 2) h(p) - n log n + O(n), where h(p) = -p logp - (1 - p) log (1 - p) is the entropy rate of a conventional memoryless binary source. Then, we propose a two-stage compression algorithm that asymptotically achieves the structural entropy up to the n log n term (i.e., the first two leading terms) of the structural entropy. Our algorithm runs either in time O(n(2)) in the worst case for any graph or in time O(n + c) on average for graphs generated by G(n,p), where c is the average number of edges. To the best of our knowledge, this is the first provable ( asymptotically) optimal graph compressor for Erds-Renyi graph models. We use combinatorial and analytic techniques such as generating functions, Mellin transform, and poissonization to establish these findings. Our experiments confirm the theoretical results and also show the usefulness of our algorithm for some real-world graphs such as the Internet, biological networks, and social networks.

关键词： Analytic information theory arithmetic encoder digital trees Erdos-Renyi graphs graph automorphism Mellin transform poissonization structural entropy unlabeled graphs

来源：评论

学校读者我要写书评

暂无评论

FPGA based EBCOT architecture for JPEG 2000

引用

MICROPROCESSORS AND MICROSYSTEMS 2005年第8-9期29卷 363-373页

作者： Gangadhar, M Bhatia, D Intel Technol India Pvt Ltd Bangalore 560017 Karnataka India Univ Texas Ctr Integrated Circuits & Syst Richardson TX 75083 USA

In this paper a high speed FPGA based implementation of Embedded Block Coding with Optimized Truncation (EBCOT) algorithm used in JPEG 2000 is proposed and implemented. The context formation engine used in EBCOT is analyzed and an architecture based on parallel processing of the three coding passes is proposed. A three stage pipelined architecture for the arithmetic encoder is used to speed up the encoding. When implemented on a XC2V1000 device, the design performs at 50 MHz after place and route. Processing time is reduced by more than 75% compared to sample based implementation and by more than 34% compared to the best architecture known. (C) 2004 Elsevier B.V. All rights reserved.

关键词： JPEG 2000 embedded block coding with optimized truncation arithmetic encoder MQ encoder FPGA

来源：评论

学校读者我要写书评

暂无评论

Analysis of Compressed Foetal Phono-Cardio-Graphy (PCG) Signals with Discrete Cosine Transform and Discrete Wavelet Transform

引用

IETE JOURNAL OF RESEARCH 2022年第4期68卷 2736-2742页

作者： Aggarwal, Vibha Gupta, Sandeep Patterh, Manjeet Singh Kaur, Lakhwinder Punjabi Univ Coll Engn & Management Neighborhood Campus Rampura Phul India Punjabi Univ Univ Coll Engn Patiala Punjab India

In the present era, precise medical instruments are available to record the medical signals for diagnosis as well as regular monitoring of pregnant lady and foetus. These recorded signals are then transmitted to the medical expert as radio signals for clinical advice. The recorded signal if transmitted without any modification, it may consume a lot of memory space and bandwidth. To address this problem, a tunable compression technique has been implemented for Foetal Phonocardiography (PCG) signal using Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT). The results show that the overall increase in compression ratio was 16.2% and 19.4%, by varying the user-defined percentage root mean square difference (UPRD) value from 0.5 to 2.0 for DCT and DWT, respectively. The performance of DWT was better as compared to DCT for Foetal PCG signals in terms of high spatial resolution in DWT.

关键词： arithmetic encoder Bisection algorithm Huffman encoder MaxLloyd quantizer Tunable compression

来源：评论

学校读者我要写书评

暂无评论

EEG SIGNAL COMPRESSION USING RADIAL BASIS NEURAL NETWORKS

引用

JOURNAL OF MECHANICS IN MEDICINE AND BIOLOGY 2004年第2期4卷 143-152页

作者： Sriraam, N. Eswaran, C. Multimedia Univ Fac Informat Technol Cyberjaya 63100 Malaysia

This paper describes a two-stage lossless compression scheme for electroencephalographic (EEG) signals using radial basis neural network predictors. Two variants of the radial basis network, namely, the radial basis function network and the generalized regression neural network are used in the first stage and their performances are evaluated in terms of compression ratio. The training is imparted to the network by using two training schemes, namely, single block scheme and block adaptive scheme. The compression ratios achieved by these networks when used along with arithmetic encoders in a two-stage compression scheme are obtained for different EEG test files. It is found that the generalized regression neural network performs better than other neural network models such as multilayer perceptrons and Elman network and linear predictor such as FIR.

关键词： Neural networks lossless compression radial basis network EEG predictor arithmetic encoder

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：