Decoders for Low Density Parity Check (LDPC) codes, used commonly in communication networks, possess inherent tolerance to random internal computation errors. Consequently, it is possible to apply voltage over-scaling...
详细信息
ISBN:
(纸本)9781450329750
Decoders for Low Density Parity Check (LDPC) codes, used commonly in communication networks, possess inherent tolerance to random internal computation errors. Consequently, it is possible to apply voltage over-scaling (VOS) in their implementation to save energy. In this paper, the impact of VOS on timing errors is characterized for a typical min sum LDPC decoder architecture using circuit simulations. Failure modes are analyzed for arithmeticcircuits performing variable and check node computations. It is shown that a rather unconventional register placement in the variable node unit is beneficial for voltage scaling, and that the check node unit may be designed such that only the least significant bits are more likely to experience errors. Insights into timing error characteristics obtained through this analysis can be used to estimate the limits of voltage scaling and associated energy saving in practical LDPC decoder designs.
暂无评论