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16th IEEE International Conference on Image Processing

作者： Mohammed, Abdul Adeel Minhas, Rashid Wu, Q. M. Jonathan Sid-Ahmed, Maher A. Univ Windsor Dept Elect Engn Windsor ON N9B 3P4 Canada

ISBN: (纸本)9781424456536

Modern fingerprint image compression and reconstruction standards used by the US Federal Bureau of Investigation (FBI) are based upon the popular 9/7 discrete wavelet transform. Multiresolution analysis tools have been successfully applied for fingerprint image compression for more than a decade;we propose a novel fingerprint image compression technique based on recently proposed wave atoms decomposition. Wave atoms decomposition has specifically been designed for enhanced representation of oscillatory patterns to convey temporal and spatial information. Our proposed compression scheme is based upon linear vector quantization of decomposed wave atoms representation of fingerprint images. Later quantized information is encoded with arithmetic entropy scheme. The proposed image compression standard outperforms the FBI fingerprint image compression standard, the wavelet scalar quantization (WSQ). Data mining, law enforcement, border security, and forensic applications can potentially benefit from our proposed compression scheme.

关键词： Image compression fingerprints wave atoms quantization arithmetic coding

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A NOVEL TRACE-PIPELINED BINARY arithmetic CODER ARCHITECTURE FOR JPEG2000

A NOVEL TRACE-PIPELINED BINARY ARITHMETIC CODER ARCHITECTURE...

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IEEE Workshop on Signal Processing Systems (SiPS 2009)

作者： Rhu, Minsoo Park, In-Cheol Korea Adv Inst Sci & Technol Taejon South Korea

ISBN: (纸本)9781424443345

Embedded block coding with optimized truncation (EBCOT) employed in the JPEG2000 standard accounts for the majority of the processing time, because the EBCOT is full of bit operations that cannot be implemented efficiently in software. The block coder consists of a bit-plane coder (BPC) followed by a binary arithmetic coder (BAC), where the most up-to-date BPC architectures are capable of producing symbols at a much higher rate than the conventional BACs can handle. This paper proposes a novel pipelined BAC architecture that can encode input symbols at a much higher rate than the conventional BAC architectures. The proposed architecture can significantly reduce the critical path delay and can achieve a throughput of 400 M symbols/sec. The critical path delay synthesized with 0.18-mu m CMOS technology is 2.42 ns, which is almost half of the delay taken in conventional BAC architectures.

关键词： EBCOT JPEG2000 VLSI architecture arithmetic coding trace scheduling

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A Fast and Fully Format Compliant Protection of JPEG2000 Code-Streams

A Fast and Fully Format Compliant Protection of JPEG2000 Cod...

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15th International Multimedia Modeling Conference

作者： Ou, Yang Sur, Chul Rhee, Kyung Hyune Pukyong Natl Univ Dept Informat Secur 599-1Daeyeon3 Dong Pusan 608737 South Korea Pukyong Natl Univ Dept Comp Sci Pukchong North Korea Pukyong Natl Univ Comp & Telecommun Engn Div Elect Pukchong North Korea

ISBN: (纸本)9783540928911

Direct encryption for the JPEG2000 code-streams by using a conventional block cipher needs an additional processing time, whereas the joint compression and encryption schemes increase the coding efficiency but with some sacrifices in security. In this paper, a Dually Randomized MQ coder (DRMQ) is presented to support both compression and encryption functionalities, and to achieve tradeoff between security and efficiency. The proposed DRMQ coder avoids the permutations of input/output bits to enhance security. It makes use of a dual randomization to provide more protected results. Furthermore, we show that the DRMQ coder can be combined with a format compliant header encryption algorithm to achieve a fast and full protection of JPEG2000 code-streams. The experimental results confirm the efficiency and encryption performance of our scheme.

关键词： JPEG2000 Joint Compression and Encryption arithmetic coding Packet Header Encryption

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A HIGH THROUGHPUT CABAC ALGORITHM USING SYNTAX ELEMENT PARTITIONING

A HIGH THROUGHPUT CABAC ALGORITHM USING SYNTAX ELEMENT PARTI...

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16th IEEE International Conference on Image Processing

作者： Sze, Vivienne Chandrakasan, Anantha P. MIT Microsyst Technol Labs Cambridge MA 02139 USA

ISBN: (纸本)9781424456536

Enabling parallel processing is becoming increasingly necessary for video decoding as performance requirements continue to rise due to growing resolution and frame rate demands. It is important to address known bottlenecks in the video decoder such as entropy decoding, specifically the highly serial Context-based Adaptive Binary arithmetic coding (CABAC) algorithm. Concurrency must be enabled with minimal cost to coding efficiency, power, area and delay. This work proposes a new CABAC algorithm for the next generation standard in which binary symbols are grouped by syntax elements and assigned to different partitions which can be decoded in parallel. Furthermore, since the distribution of binary symbols changes with quantization, an adaptive binary symbol allocation scheme is proposed to maximize throughput. Application of this next generation CABAC algorithm on five 720p sequences shows a throughput increase of up to 3x can be achieved with negligible impact on coding efficiency (0.06% to 0.37%), which is a 2 to 4x reduction in coding penalty compared with H.264/AVC and entropy slices. Area cost is also reduced by 2x. This increased throughput can be traded-off for low power consumption in mobile applications.

关键词： arithmetic coding Parallel Processing

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An Efficient Lossless Compression Algorithm for Bayer Pattern Images

An Efficient Lossless Compression Algorithm for Bayer Patter...

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International Conference on Wireless Communications and Signal Processing

作者： Xiao, Yuwei Cheng, Peiyan Shanxi Univ Finance & Econ Sch Informat Management Taiyuan Peoples R China Shanxi Univ Finance & Econ Taiyuan Peoples R China

ISBN: (纸本)9781424448562

In this paper, we propose an effective sequential lossless compression scheme which performs sequentially pixel by pixel in raster-scan order. The proposed method has three major components: a causal interpolation module, a fixed predictor and context based adaptive arithmetic coder. The causal interpolation module estimates the values of past pixels in the context which are the same color as current predicted pixel. The predictor which is based on IF-THEN structure exploits structural redundancies between mosaic-like color components, and its residuals are well-modeled by a two-side geometry distribution centered at zero. An advantage of the proposed compression method is the clear separation between prediction and entropy coding of prediction errors. Finally, an effective and efficient arithmetic coder can be easily interfaced with our predictor. Experimental results show that our method outperforms all other evaluated schemes in all testing images in term of bit-rate while maintains modest complexity level.

关键词： Image Lossless Compression Causal Interpolation arithmetic coding

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Three-Dimensional Binary-Uncoded Video Compression using 3DSPIHT-ZTR

Three-Dimensional Binary-Uncoded Video Compression using 3DS...

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International Conference on Intelligent Human-Machine Systems and Cybernetics

作者： Chia, Wai Chong Ang, Li-Minn Seng, Kah Phooi Univ Nottingham Sch Elect & Elect Engn Jalan Broga 43500 Selangor Darul Malaysia

ISBN: (纸本)9780769537528

In conventional video coding, motion compensation is commonly being used to remove the temporal redundancy. But the computational complexity introduced by the motion compensation can he very high, especially when the full search is adopted. The 3DSPIHT resolves this problem by replacing the motion compensation with the temporal wavelet transform, which require lower computational complexity. However, the performance of the 3DSPIHT is optimal only when arithmetic coding (AC) is incorporated. This contradicts the initial idea of reducing the computational complexity with the wavelet transform, because the computational complexity introduced by AC is sufficiently high. In this paper, an efficient binary-uncoded algorithm for video coding called the 3DSPIHT-ZTR is proposed. The idea is to re-introduce the use of ZTR symbol, which is initially used in the Embedded Zerotree Wavelet (EZW) algorithm, into 3DSPIHT. In addition, the significant offspring are also encoded in a slightly different way to further enhance the performance. The performance of 3DSPIHT-Z'I'R is approximately 1.5 dB better than the conventional 3DSPIHT in terms of PSNR. Its performance is also comparable to 3DSPIHT with AC under certain circumstances.

关键词： 3DSPIHT arithmetic coding Binary-Uncoded EZW Video coding

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arithmetic coding in parallel

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INTERNATIONAL JOURNAL OF FOUNDATIONS OF COMPUTER SCIENCE 2005年第6期16卷 1207-1217页

作者： Supol, J Melichar, B Czech Tech Univ Fac Elect Engn Dept Comp Sci & Engn Prague 12135 2 Czech Republic

We present an EREW PRAM cost optimal parallel algorithm for arithmetic coding computation. We solve the problem in 0(log n) time using n/log n processors. Each part of the algorithm as well as a well-known parallel pr... 详细信息

关键词： arithmetic coding EREW PRAM NC algorithm parallel prefix computation parallel text compression

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Finite-precision arithmetic coding via index-splitting and probability-fitting

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APPLIED MATHEMATICS AND COMPUTATION 2005年第2期167卷 976-995页

作者： Chan, DY Ku, CY Natl Chiayi Univ Dept Comp Sci & Informat Engn Chiayi Taiwan Natl Chung Cheng Univ Dept Informat Management Chiayi Taiwan

This paper proposes a fitting-by-splitting algorithm (abbreviated as the FS algorithm), which is composed of an index-splitting (IS) algorithm and a probability-fitting (PF) algorithm, to effectively achieve the finite-precision arithmetic coding code named as the FS-AC code. The FS algorithm generates the FS-AC codes of arbitrarily specified length without the need of post-appended sentinel symbol or pre-affixed side-information bits. Its IS process can split the input symbols into paired indices to make the residual information space be reused as effectively as possible at the end of arithmetically encoding a fixed-precision code. And, the PF process performs after each IS operation for enhancing the reuse efficiency via a fast adaptation process of probability table. Through the integration of IS and PF processes, not only the coding efficiency of proposed finite-precision AC codec can be close to that of unlimited precision AC codec especially for our proposed binary AC codecs. And also, consecutive FS-AC codes can be mutually independent such that the error propagation can be almost blocked to an AC code in problem. Hence, our new AC codecs can be appropriate for generating finite-precision AC codes in the high-speed networks. (c) 2004 Elsevier Inc. All rights reserved.

关键词： arithmetic coding binary arithmetic coding index-splitting

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Approximate arithmetic coding for bus transition reduction in low power designs

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2005年第6期13卷 696-707页

作者： Lekatsas, H Henkel, J Wolf, W NEC Labs Amer Inc Princeton NJ 08540 USA Univ Karlsruhe D-76128 Karlsruhe Germany Princeton Univ Dept Elect Engn Princeton NJ 08540 USA

We present a method for reducing the power consumption of compressed-code systems by selectively inverting bits that are transmitted on the bus. By incorporating bus inversion into code compression/decompression, we reduce power consumption with no cost in hardware or power relative to code compression without inversion. Inverting has to be done carefully to ensure that the codes can still be decoded. As an additional challenge, compression will generally increase bit-toggling as it removes redundancies from the code transmitted. Therefore, we need to find the right balance between compression ratio and bit-toggling reduction. This paper presents a suitable algorithm that will combine approximate compression techniques with bit-toggling reduction and will explore the various tradeoffs. We take advantage of the approximations introduced to modify codes and reduce bit-toggling, while maintaining compression performance and decoding speed. An interesting result that is derived from our work is that high compression ratios do not necessarily result in the lowest power consumption. By using our method, bus-related power consumption has been reduced by as much as 35% compared to a system with no compression, and as much as 14% compared to a compressed-code system. Bit-toggling reduction does not impose any additional hardware costs other than the decompression engine. We also present a detailed analysis on how bus widths affect bit-toggling when transmitting compressed code, and we show experimental results on ARM, MIPS, and SPARC code. We finally compare our work with Bus Invert and show results that are superior except for the random data case where Bus Invert performs better.

关键词： arithmetic coding code compression low power design

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A configurable statistical lossless compression core based on variable order Markov modeling and arithmetic coding

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IEEE TRANSACTIONS ON COMPUTERS 2005年第11期54卷 1345-1359页

作者： Nunez-Yanez, JL Chouliaras, VA Univ Bristol Dept Elect & Elect Engn Bristol BS8 1UB Avon England Univ Loughborough Dept Elect & Elect Engn Loughborough LE11 1TU Leics England

This paper presents a practical realization in hardware of the concepts of variable order Markov modeling using multisymbol alphabets and arithmetic coding for lossless compression of universal data. This type of statistical coding algorithm has long been regarded as being able to deliver very high compression ratios close to the information content of the source data. However, their high computational complexity has limited their practical application in embedded environments such as in mobile computing and wireless communications. In this paper, a hardware amenable algorithm named PPMH and based on these principles has been developed and its architecture and implementation detailed. This novel lossless compression core offers innovative solutions to the computational issues in both stages of modeling and coding and delivers high compression efficiency and throughput. The configurability features of the core allow efficient use of the embedded SRAM present in modern FPGA technologies where memory resources range from a few kilobits to several megabits per device family. The core has been targeted to the Altera Stratix FPGA family and performance, coding efficiency, and complexity measured for different memory configurations.

关键词： Markov modeling statistical compression lossless compression arithmetic coding

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