High-end microprocessors now tend to be superscalar, to execute operations out of order, and to support shared memory among multiple processors. Verifying the functionality of such a microprocessor using simulation re...
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High-end microprocessors now tend to be superscalar, to execute operations out of order, and to support shared memory among multiple processors. Verifying the functionality of such a microprocessor using simulation requires many stages, from tests of simple portions of the design, through simple tests of a single processor to complex tests of multiple processors. We followed this strategy using some already existing tools and writing some new tests and tools. We describe in this paper the general strategy and the tool set we created to perform the final simulation stage of design verification: running complex tests on a model of a multiprocessor system. This tool set operates on the principle that tests which mimic real programs are more likely to uncover errors that customers would encounter. Our results show that random realistic tests can get better coverage of common multiprocessor scenarios in fewer cycles than purely random tests.< >
Issues of logic-based program transformation are discussed, and a method for transforming a source program expressed as a set of extended Horn clauses into a target program in an Algol-like procedural language is pres...
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Issues of logic-based program transformation are discussed, and a method for transforming a source program expressed as a set of extended Horn clauses into a target program in an Algol-like procedural language is presented. The potential applications of this transformation method include (1) automatic synthesis of programs from design specifications which are either written in or translatable into extended Horn logic clauses, (2) adaptation of existing logic programs to a procedural execution environment in order to improve execution efficiency or facilitate reusability of the software, and (3) support of a hybrid-programming environment.< >
Most recent theoretical literature on program obfuscation is based on notions like virtual black box (VBB) obfuscation and indistinguishability obfuscation (iO). These notions are very strong and are hard to satisfy. ...
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ISBN:
(数字)9781665403924
ISBN:
(纸本)9781665403931
Most recent theoretical literature on program obfuscation is based on notions like virtual black box (VBB) obfuscation and indistinguishability obfuscation (iO). These notions are very strong and are hard to satisfy. Further, they offer far more protection than is typically required in practical applications. On the other hand, the security notions introduced by software security researchers are suitable for practical designs but are not formal or precise enough to enable researchers to provide a quantitative security assurance. Hence, in this paper, we introduce a new formalism for practical program obfuscation that still allows rigorous security proofs. We believe our formalism will make it easier to analyse the security of obfuscation schemes. To show the flexibility and power of our formalism, we give a number of examples. Moreover, we explain the close relationship between our formalism and the task of providing obfuscation challenges.
Describes the design of a language for automatically generating programs to reformat HL7 messages. The clinical information system (CIS) at Columbia-Presbyterian Medical Center (CPMC) uses HL7 as a standard for data i...
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Describes the design of a language for automatically generating programs to reformat HL7 messages. The clinical information system (CIS) at Columbia-Presbyterian Medical Center (CPMC) uses HL7 as a standard for data interchange. Collecting data from several different ancillaries necessitates reformatting the information to provide a uniform data representation for the CIS. We developed a system that automatically generates HL7 reformatters given a specification of operations that need to be performed on the third-party messages. This automatic generation significantly reduces the development time; we expect it to have a major impact on the maintenance of these programs as well.
In this paper a mono-objective optimum design procedure for parallel robot is outlined by using optimality criterion of workspace and numerical aspects. A mono-objective optimization problem is formulated by referring...
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In this paper a mono-objective optimum design procedure for parallel robot is outlined by using optimality criterion of workspace and numerical aspects. A mono-objective optimization problem is formulated by referring to a basic performance of parallel robots. Additional objective functions can be used to extend the proposed design procedure to more general but specific design problems. A kinematic optimization was performed to maximize the workspace of the mini parallel robot. Optimization was performed using genetic algorithms
Statistical analysis of bug discovery data is used in the software industry to check the quality of the testing process and estimate the reliability of the tested program. In this paper, we show that the same techniqu...
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Statistical analysis of bug discovery data is used in the software industry to check the quality of the testing process and estimate the reliability of the tested program. In this paper, we show that the same techniques are applicable to hardware design verification. We performed a study on two implementations of state-of-the-art PowerPC processors that shows that these techniques can provide quality information on the progress of verification and good predictions of the number of bugs left in the design and the future MTTF.
Hardware/software codesign requires an accurate way of evaluating candidate architectures. Architecture exploration (which can be used to automate hardware/software codesign) requires an automatic way of evaluating ca...
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Hardware/software codesign requires an accurate way of evaluating candidate architectures. Architecture exploration (which can be used to automate hardware/software codesign) requires an automatic way of evaluating candidate architectures, otherwise a substantial programming effort must be expended on each iteration. We present a system that automatically generates an instruction level simulator (ILS) and a hardware implementation model given a description of a candidate architecture. Accurate cycle counts can be obtained for specific applications using the ILS. At the same time, the hardware implementation model can be used to obtain cycle length, die size, and power consumption estimates. These measurements allow an accurate performance evaluation to be constructed for each candidate architecture. We use the machine description language ISDL to support the generation of the ILS and the hardware model, as well as other tools which form the core of our hardware/software codesign system.
The author traces the development history of one program generator, and then reviews the constraints inherent in a very simple network definition of the system logic. Alternative solutions for strengthening the system...
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The author traces the development history of one program generator, and then reviews the constraints inherent in a very simple network definition of the system logic. Alternative solutions for strengthening the system features are presented. Distributed processing, with the network as one of several nodes, is suggested as a unifying solution. The implementation of this approach is considered, and the progress made in this area is reported.< >
We are interested in how to expose our students to test driven development (TDD) and have experimented with a variety of ways of leveraging testing technology to help our students learn to program in our first program...
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We are interested in how to expose our students to test driven development (TDD) and have experimented with a variety of ways of leveraging testing technology to help our students learn to program in our first programming course. Initially, we developed a framework that allows the students to run tests that are developed by the faculty member. That experience led us to developing a JUnit plug-in that allowed the students to specify the tests without having to write the test code. As a result of these experiences, we have re-structured this class into these roughly sequential phases: learning to read code, learning to write code, and learning to program. Throughout this course, the students are using TDD, writing their own JUnit tests, and refactoring as they develop their code iteratively. This change has been made without dropping any of the required course content.
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