Although object-oriented languages can improve programming practices, their characteristics may introduce new problems for software engineers. One important problem is the presence of implicit control flow caused by e...
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ISBN:
(纸本)9780769521633
Although object-oriented languages can improve programming practices, their characteristics may introduce new problems for software engineers. One important problem is the presence of implicit control flow caused by exception handling and polymorphism. Implicit control flow causes complex interactions, and can thus complicate software-engineering tasks. To address this problem, we present a systematic and structured approach, for supporting these tasks, based on the static and dynamic analyses of constructs that cause implicit control flow. Our approach provides software engineers with information for supporting and guiding development and maintenance tasks. We also present empirical results to illustrate the potential usefulness of our approach. Our studies show that, for the subjects considered, complex implicit control flow is always present and is generally not adequately exercised.
We present a survey of the current proposed countermeasures against distributed denial of service (DDoS) attacks that give a promising approach to the field. We also state the weaknesses of the above methods which res...
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We present a survey of the current proposed countermeasures against distributed denial of service (DDoS) attacks that give a promising approach to the field. We also state the weaknesses of the above methods which result to the fact that no unified method has been adopted yet. We also make a discussion about the future trends in DDoS defense.
Current haptic application development tools typically require considerable programming efforts in order to make an existing surface-based graphical virtual environment (G-VE) touchable. In this paper we describe a gr...
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Current haptic application development tools typically require considerable programming efforts in order to make an existing surface-based graphical virtual environment (G-VE) touchable. In this paper we describe a graphics-to-haptics (G/sub 2/H) tool that provides a framework for developing the largest possible haptic virtual environments (H-VE) for stable haptic applications. G/sub 2/H automatically converts a G-VE into a haptic application with no additional programming via a real-time visual software development process of 1) importing G-VEs, 2) setting haptic and visual properties for models, 3) selecting graphics and haptic rendering algorithms, 4) representing the haptic device position in the virtual space, 5) interfacing different haptic devices to the virtual environment, and 6) testing and modify the virtual environment to ensure real-time stability of the created haptic application. The tested H-VE can be used as the foundation for other applications such as surgical simulators [Acosta, E et al., (2004), (2002)].
Verification has indisputably become the primary challenge today with recent industry studies estimating that half of all chips manufactured require one or more re-spins. Ideally the performance of the design should b...
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Verification has indisputably become the primary challenge today with recent industry studies estimating that half of all chips manufactured require one or more re-spins. Ideally the performance of the design should be verified for all possible circumstances under which it might be operated in the real world. Unfortunately, it requires a long time to generate and run test sequences. Under the time to market pressure, it is very time consuming to write all test programs manually. This brings about the necessity of developing a random test program generator (RTPG). Proposed RTPG is for verifying the SPARC processor architecture. The approach is in classifying general type of bugs that can get into the EXU unit of SPARC T1 processor design and introducing design defects in the RTL. Several defective models are developed covering the entire functional blocks in the EXU and several coverage models for the test cases run on the defective design were also developed. The direct and random test case generation is applied on the buggy model and various coverage reports are analyzed. This work tends to look back at the fact that verification is a process that is never truly complete. We understand that designs are error-prone and so, the objective of verification is to detect the errors. Yet, no one can really prove that the design is error-free.
This paper describes an extended hybrid automata approach and design according to its architecture of a program generator for data acquisition and control system and its applications for huge industrial objects. It pr...
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This paper describes an extended hybrid automata approach and design according to its architecture of a program generator for data acquisition and control system and its applications for huge industrial objects. It presents some new concepts, results and analyses oriented design and implementation of component-oriented program configurators oriented mostly to real-time applications. The described two level graph representation model implements extended Moore automaton enabling implementation of hybrid (analogue and discreet) data processing.
As the complexity of high-performance microprocessor increases, functional verification becomes more difficult and emerges as the bottleneck of the design cycle. In this paper, we suggest a functional verification met...
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ISBN:
(纸本)0780336623
As the complexity of high-performance microprocessor increases, functional verification becomes more difficult and emerges as the bottleneck of the design cycle. In this paper, we suggest a functional verification methodology, especially for the compatible microprocessor design. To guarantee the perfect compatibility with previous microprocessors, we developed three C models in different representation levels, i.e., Polaris, MCV(Micro-Code Verifier) and StreC. C models are co-simulated with consistency checking between two different models. The simulation speed of C models makes it possible to test the "real-world" application programs on the RTL design with a software board model. To increase the confidence level of verifications, Profiler reports the verification coverage of the test vector, which is fed back to the automatic test program generator. Restartability feature also helps significantly reduce the total simulation time. Using the proposed verification methodology, we designed and verified an Intel 486-compatible microprocessor successfully.
Non-circular gears meshing with the characteristics of checkmark, it requires non-circular gears should meshing at the zero line accurately at the beginning of processing. So, there should be a starting point when set...
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Non-circular gears meshing with the characteristics of checkmark, it requires non-circular gears should meshing at the zero line accurately at the beginning of processing. So, there should be a starting point when setting cutter in the processing of non-circular gears. This point can ensure strict position relation between cutter and workpiece. To strictly ensure strict position relation, how to accurately determine the coordinates of the cutter center position is the key problem. How to determine the coordinates of the cutter center position were analyzed when hobbing non-circular gear with CNC gear hobbing machine, and some related formulas was derived. Formulas be derived are not only valid for non-circular gear, but also are applicable to cylindrical gears. It is easy to calculate and determine the coordinates of the cutterl center, and provides theoretical basis for the establishment of library operations in automatic programming system.
Web services offer a number of valuable features towards supporting the development of open distributed systems, built out of the composition of autonomous services. Nonetheless, the resulting systems must offer a num...
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Web services offer a number of valuable features towards supporting the development of open distributed systems, built out of the composition of autonomous services. Nonetheless, the resulting systems must offer a number of non-functional properties and in particular dependability-related ones, for acceptance by users, including effective exploitation in the e-business domain. However, dependability of composite services can only be achieved according to the recovery property of composed Web services. This calls for the rigorous specification of the standard and exceptional behavior of Web services. This paper introduces the WS-RESC conversation language that addresses this issue. In a way similar to existing conversation languages, WS-RESC includes constructs for defining ordering and choices. However, WS-RESC further includes constructs for specifying concurrency since it is an inherent feature of distributed systems, and for specifying timing constraints and recovery properties of conversation since these are key behavioral properties in the context of dependability.
A fourth-generation analog in-circuit program generator (APG) is described. A custom hybrid behavioral/nodal simulator using Monte Carlo statistical analysis is shown to provide high-quality tests that require a minim...
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A fourth-generation analog in-circuit program generator (APG) is described. A custom hybrid behavioral/nodal simulator using Monte Carlo statistical analysis is shown to provide high-quality tests that require a minimum of debug and long-term maintenance while maximizing test portability. After over a year of use, this APG has shown, on many occasions, to give analog turn-on rates of 98% to 100%. This is a significant improvement over previous generations. This high turn-on has reduced the amount of debug and maintenance time significantly. The validity of the model was demonstrated when its results were major input in setting the tester specifications. Those results were confirmed by extensive environmental and performance verification. The need for accurate test limits for analog in-circuit tests is shown.< >
The authors present theory, design and measurement results for an online histogram equalization algorithm implemented on a 750MS/s 6b flash analog to digital converter in standard 0.35 μ m CMOS. The user simply turns...
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The authors present theory, design and measurement results for an online histogram equalization algorithm implemented on a 750MS/s 6b flash analog to digital converter in standard 0.35 μ m CMOS. The user simply turns on "training mode" for a few seconds, while the algorithm automatically adjusts comparator levels to match the observed input signal distribution. This results in signal conversion with equal probability for each of the output codewords. The new architecture is an extension of a flash ADC incorporating an adaptive floating gate comparator and control circuits for automatic programming of the reference levels. Experiments show output codes with at least 5.9 bits entropy for ramp, sine and Gaussian random signals after adaptation. Uniform programming produces 5.7 ENOB for input frequencies up to 200MHz and maximum DNL and INL of 0.24 LSB and 0.79 LSB at Nyquist rate, while equalization produces 5.3 ENOB up to 600MHz.
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