In distributed system it may pose some problems to visualize the exact nature of functioning and the sequence of events in various nodes of the said system and such insights are essential to comprehend and analyze the...
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ISBN:
(纸本)9781728102603
In distributed system it may pose some problems to visualize the exact nature of functioning and the sequence of events in various nodes of the said system and such insights are essential to comprehend and analyze the behavior of different algorithms executing in different nodes of the system mentioned. This paper describes a framework that has been implemented to help visualize and analyze the working behavior of various algorithms on distributed system. Using this platform it is possible for students and researchers to gain insight into the working of various nodes of a distributed system, check their interactions at run time and thus to test different algorithms in a simulated as well as actual environment. The framework lets the student to check the behavior of certain standard built-in distributed algorithms, viz., Leader Election using Bully and Ring Algorithms, Ricart-Agrawala's Mutual Exclusion Algorithm and Chandy-Mishra-Hash deadlock detection algorithm. The users can also write their own algorithms and use a program generator module to generate programs for different nodes using this framework. Subsequent to the execution, a graphical analyzer module aids the user by showing the execution behavior of the algorithm using a space-time graphical diagram that makes use of Lamport's Time Stamping algorithm. The framework provides built-in system-level supports to facilitate exclusive access to shared resources and detects distributed deadlock also.
Supporting the assessment of an ever-increasing number of students is an error-prone and resource intensive process. Computer based assessment (CBA) software aids educators by automating aspects of the assessment of s...
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Supporting the assessment of an ever-increasing number of students is an error-prone and resource intensive process. Computer based assessment (CBA) software aids educators by automating aspects of the assessment of student work. Using CBA benefits pedagogically and practically both students and educators. The Learning Technology Group at the University of Nottingham has been actively researching, developing and using software to automatically assess programming coursework for 14 years. Two of the systems developed, Ceilidh and its successor CourseMaster, are being used by an increasing number of academic institutions. Research has resulted in a system for supporting the full lifecycle of free-response CBA that has diagram-based solutions. The system, DATsys, is an authoring environment for developing diagram-based CBA. It has been designed to support the authoring of coursework for most types of diagram notations. Exercises have been developed and tested for circuit diagrams, flowcharts and class diagrams. Future research plans are for authoring exercises in many more diagram notations.
Using UNITY as a model for asynchronous hardware systems, we give a generic specification of a device that obeys a four phase protocol. The specification is general enough to allow devices with bundled data as well as...
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Using UNITY as a model for asynchronous hardware systems, we give a generic specification of a device that obeys a four phase protocol. The specification is general enough to allow devices with bundled data as well as dual-rail coded ports, and two phase signalling can be seen as a special case. We give a generic implementation of a function cell and show that A. Martin's Adder cell is an instance. Finally, we prove two composition theorems that allow four phase devices to be combined into larger four phase devices. All stated theorems were checked using a mechanical theorem prover and we give complete definitions for all the concepts used in the generic specification.
We represent concurrent processes as Boolean propositions or gates, cast in the role of accepters of concurrent behavior. This properly extends other mainstream representations of concurrent behavior such as event str...
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We represent concurrent processes as Boolean propositions or gates, cast in the role of accepters of concurrent behavior. This properly extends other mainstream representations of concurrent behavior such as event structures, yet is defined more simply. It admits an intrinsic notion of duality that permits processes to be viewed as either schedules or automata. Its algebraic structure is essentially that of linear logic, with its morphisms being consequence-preserving renamings of propositions, and with its operations forming the core of a natural concurrent programming language.< >
The irregular ventricular (V) rate of atrial fibrillation (AF) may contribute to adverse hemodynamics and symptoms. An algorithm that adjusts pacing rate based on RR interval mean absolute difference (MADIFF) to reduc...
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The irregular ventricular (V) rate of atrial fibrillation (AF) may contribute to adverse hemodynamics and symptoms. An algorithm that adjusts pacing rate based on RR interval mean absolute difference (MADIFF) to reduce AF V rate variability was tested. Previous algorithms used a fixed % of V pacing to change pacing rate. Patients with chronic AF, intact AV nodal conduction, and a pacemaker were studied during V rate stabilization (VRS) pacing and control. Previous work showed that cardiac output was inversely related to the % of RRs which were short relative to the preceding RR. VRS eliminated 74% and 81% of cycles more than 10% and 20% shorter than the preceding RR interval. MADIFF was better correlated to the % of cycles more than 10% and 20% less than the preceding RR than was % pacing. Hence, a MADIFF-based VRS algorithm reduced the % of short RRs and may be a better indicator/controller of hemodynamic performance in AF than % pacing.
This paper analyzes corewar, a very peculiar computer game popular in mid 80's where different programs fight in the memory of a virtual computer. The /spl mu/GP, an evolutionary assembly-program generator, is use...
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This paper analyzes corewar, a very peculiar computer game popular in mid 80's where different programs fight in the memory of a virtual computer. The /spl mu/GP, an evolutionary assembly-program generator, is used to evolve efficient programs, and the game is exploited to evaluate new evolutionary techniques. The paper introduces a new migration model that exploits the polarization effect and a new hierarchical coarse-grained approach applicable whenever the final goal can be seen as a combination of semi-independent sub goals. Additionally, two very general enhancements are proposed. Analyzed techniques are orthogonal and broadly applicable to different real-life contexts. Experimental results show that all these techniques are able to outperform a previous approach.
This system for mixed-signal/analog integrated circuits is divided into off-line test program development process and on-line test application process. During the off-line development phase, generated test programs ar...
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ISBN:
(纸本)0780336941
This system for mixed-signal/analog integrated circuits is divided into off-line test program development process and on-line test application process. During the off-line development phase, generated test programs are described by using HDL-A and simulation tools, and validated by a test system interfacing the unit under test, where Labview, a general-purpose programming tool, is used as a virtual instrument.
Choreography description languages specify interactions among a set of services from a global point of view. From this description, it is possible to generate either an orchestrator (centralized interactions), or a se...
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Choreography description languages specify interactions among a set of services from a global point of view. From this description, it is possible to generate either an orchestrator (centralized interactions), or a set of peers or wrappers (distributed interactions). In this paper, we present first a model of service protocols with value passing, and an abstract choreography language to describe their composition and adaptation. Adaptation is useful while composing services to correct existing mismatches which might exist between their interfaces. Given abstract descriptions of services and their choreography, we propose techniques based on encodings into process algebra to generate an orchestrator and a set of wrapper protocols. Generation of wrappers is particularly tackled in this paper because this enables the system deployment in the context of distributed systems, and keeps at the same time a full parallelism of the system execution. Our approach is completely automated by a prototype tool we implemented.
automatic bitwidth analysis is a key ingredient for highlevel programming of FPGAs and high-level synthesis of VLSI circuits. The objective is to find the minimal number of bits to represent a value in order to minimi...
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automatic bitwidth analysis is a key ingredient for highlevel programming of FPGAs and high-level synthesis of VLSI circuits. The objective is to find the minimal number of bits to represent a value in order to minimise the circuit area and to improve efficiency of the respective arithmetic operations, while satisfying user-defined numerical constraints. We present a novel approach to bitwidth- or precision-analysis for floating-point designs. The approach involves analysing the dataflow graph representation of a design to see how sensitive the output of a node is to changes in the outputs of other nodes: higher sensitivity requires higher precision and hence more output bits. We automate such sensitivity analysis by a mathematical method called automatic differentiation, which involves differentiating variables in a design with respect to other variables. We illustrate our approach by optimising the bitwidth for two examples, a discrete Fourier transform (DFT) implementation and a Finite Impulse Response (FIR) filter implementation.
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