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17th IEEE Latin-American test Symposium (LATS)

作者： Jasnetski, Artjom Ubar, Raimund Tsertov, Anton Tallinn Univ Technol Dept Comp Engn Tallinn Estonia

ISBN: (纸本)9781509013319

Software-Based Self-testing (SBST) is a well-known non-intrusive method for testing microprocessors. This paper presents an approach for automatic SBST program generation, based on the methodology of using High-Level Decision Diagrams (HLDD) for modeling microprocessors and faults. The novelty of this approach is that Instruction Set Architecture (ISA) of the processor is the only needed input data for the automated test program generator.

关键词： microprocessor test software-based self-test (SBST) automatic test program generation high-level decision diagrams

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automatic PRODUCTION OF THE PSEUDOCIRCUIT BOOLEAN FOR THE FAILURE BOUNDS ANALOG DIAGNOSIS SCHEME

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ELECTRONICS LETTERS 1990年第17期26卷 1377-1378页

作者： GARRETT, C Dept. of Electr. & Electron. Eng. Brighton Polytech. UK

A basic for partial automation of the failure bounds analogue diagnosis method is given by Wu and Wu. An extension to their work which enables the complete pseudo-circuit to be simulated using any commercial simulator (in this case SPICE) is described. The pseudo-circuit is formed in such a way as to require only a simple comparison to produce the intermediate Boolean diagnosis state vector, prior to use within the failure bounds decision algorithm.

关键词： SPICE automatic test program generation circuit analysis computing failure bounds analogue diagnosis method failure bounds analogue diagnosis scheme pseudo circuit Boolean production simulation

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NEW MEASURES OF testABILITY AND test COMPLEXITY FOR LINEAR ANALOG FAILURE ANALYSIS

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IEEE TRANSACTIONS ON COMPUTERS 1981年第11期30卷 884-888页

作者： PRIESTER, RW CLARY, JB Systems and Measurements Division Research Triangle Institute

The failure analysis of analog electronic systems is characterized by numerous, difficult problems. Assessing the testability and test complexity of a given system is one such problem. In fact, robust, quantitative measures of these important features have not been available to the analog testing community. This paper introduces new measures for both testability and test complexity which: 1) are quantitative, 2) are capable of handling multiple faults, and 3) have a well-defined interpretation. These measures are based upon published results from optimal experiment designs as developed in the discipline of systems identification. Parameter testability is defined in terms of information (in the sense of Fisher) return, while test complexity is functionally related to the experiment time required to achieve specified accuracy with regard to the uncertain parameters of interest. Thus both of the new measures introduced depend, not only upon the specific system at hand, but also upon the experimental conditions used in performing the tests. The results of this approach lead to quantitative measures that have optimality features based upon the Cramer–Rao bound.

关键词： automatic test program generation fault diagnosis experiment design test complexity measure test point allocation testability measure

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Code generation for functional validation of pipelined microprocessors

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JOURNAL OF ELECTRONIC testING-THEORY AND APPLICATIONS 2004年第3期20卷 269-278页

作者： Corno, F Sanchez, E Reorda, MS Squillero, G Politecn Torino Dipartimento Automat & Informat Turin Italy

Functional validation of pipelined microprocessors is a challenging task, as the behavior of a pipeline is determined by a sequence of instructions and by the interaction between their operands. This paper describes an approach to automatic test-program generation based on an evolutionary algorithm. The proposed methodology is able to tackle complex pipelined designs. Human intervention is limited to the formalized listing of the instruction set, and also internal parameters of the test program generator are auto-adapted. A prototype was built and exploited to generate test programs for the DLX/pII, a pipelined microprocessor. For the purpose of these experiments, test programs were devised trying to maximize the RT-level statement coverage. However, the method can be used to generate test programs on different target metrics. Results show the feasibility and effectiveness of the method.

关键词： functional validation automatic test program generation evolutionary algorithms pipelined micro processors

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The Pseudo-code representation of test Resources and test Requirements in ATML 6

The Pseudo-code representation of Test Resources and Test Re...

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6th International Conference on Information Science and Control Engineering (ICISCE)

作者： Fan Shuyi Wei Baohua Jiang Huixia Army Engn Univ Shijiazhuang Campus Shijiazhuang Hebei Peoples R China

ISBN: (数字)9781728157122

ISBN: (纸本)9781728157122

The ATML documents are used to describe test information and are represented in XML format. We can consider using computer to automatically identify and extract relevant test information in the document, based on which the test program of the test system can be automatically generated. Therefore, it is necessary to analyze the documents that representing the elements of the test system to determine the pseudo-code representation of these elements, so as to facilitate the automatic generation of test programs. This paper analyses the test capability of test instruments in ATML test description document and the test requirements of UUT, as well as the cable connection between ATE, ITA and UUT. On this basis, the data structures of connectors, ports, resources, switches, capabilities and cable connections are defined, which lays the foundation for automatic generation of test programs.

关键词： ATML Pseudo-code automatic test program generation test resources test Requirements

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Automated Software-Based Self-test generation for Microprocessors 24

Automated Software-Based Self-Test Generation for Microproce...

引用

24th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)

作者： Jasnetski, Artjom Ubar, Raimund Tsertov, Anton Tallinn Univ Technol Dept Comp Engn Tallinn Estonia

ISBN: (纸本)9788363578121

Software-based self-testing (SBST) is a well-known non-intrusive method for testing microprocessors. This paper presents a tool for automated Software-Based Self-test program generation. The tool is based on the previously published methodology of using High-Level Decision Diagrams (HLDD) for modeling microprocessors and faults. The tool generates from the Instruction Set Architecture of the processor its HLDD model and using the formalism of the HLDD model, together with beforehand prepared code templates, generates the final self-test program. The functionality of the tool is demonstrated by carrying out experimental research on test generation for the 8-bit microprocessor PARWAN and the 32-bit SPARCv8 microprocessor Leon 3. In combination with the fault simulation tools, it is a novel solution for SBST program generation. The experimental results demonstrate the advantages of the implemented method in comparison with previously published results.

关键词： microprocessor software-based self-test (SBST) automatic test program generation high-level decision diagrams (HLDD) synthesis

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I_DDQ testing in CMOS digital ASICs

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Journal of Electronic testing 1992年第4期3卷 317-325页

作者： Perry, Roger Storage Technology Corporation Louisville 80028-5110 CO 2270 South 88th Street United States

IDDQ testing with precision measurement unit (PMU) was used to eliminate early life failures caused by CMOS digital ASICs in our products. Failure analysis of the rejected parts found that bridging faults caused by pa... 详细信息

I_DDQ testing with precision measurement unit (PMU) was used to eliminate early life failures caused by CMOS digital ASICs in our products. Failure analysis of the rejected parts found that bridging faults caused by particles were not detected in incoming tests created by automatic test generation (ATG) for stuck-at-faults (SAF). The nominal 99.6% SAF test coverage required to release a design for production was not enough! This article shows how I_DDQ testing and supplier process improvements affected our early life failure rates over a three year period. A typical I_DDQ measurement distribution, effects of multiple I_DDQ testing, and examples of the defects found are presented. The effects of less than 99.6% fault coverage after the I_DDQ testing was implemented are reviewed. The methods used to establish I_DDQ test limits and implement the I_DDQ test with existing ATG testing are included. This article is a revision of one given at International test Conference [1]. © 1992 Kluwer Academic Publishers.

关键词： automatic test program generation bridging fault early life failures IDDQ current stuck-at fault

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